Abstract: A method for integrating buffer views into buffer access operations in a reconfigurable computing environment includes detecting, in an instruction stream for a reconfigurable dataflow unit (RDU), a buffer allocation statement comprising a tensor indexing expression, a buffer view indicator and one or more buffer view parameters. The method also includes lowering the buffer view parameters into the indexing expression according to the buffer view indicator to produce a modified tensor indexing expression, removing the buffer view indicator from the buffer allocation statement to produce a modified buffer allocation statement and allocating a buffer according to the modified buffer allocation statement. The modified buffer allocation statement may include the modified tensor indexing expression. A corresponding system and computer readable medium are also disclosed herein.

Abstract: Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

Abstract: A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.

Abstract: A communication device includes controller circuitry and transmitter circuitry. The controller circuitry determines a number of strings of consecutive ones in a data packet, and determines a number of stuffed bytes based on the number of strings of consecutive ones. Further, the controller circuitry schedules a transaction packet to be transmitted within a bus interval based on a determination that a total number of bytes of the transaction packet is less than a number of available bytes in the bus interval. The total number of bytes of the transaction packet is based on a number of payload bytes of the data packet and the number of stuffed bytes. The transmitter circuitry transmits the transaction packet during the bus interval based on the controller circuitry scheduling the transaction packet for transmission.

Abstract: A switch is described. The switch includes a plurality of ports, a plurality of port logic modules, a memory, and a switch fabric. Transactions ingress and egress the switch via the ports. The port logic modules are coupled with the ports. Each port logic module has core clock domain logic for a core clock domain specific to a corresponding port. The memory includes banks. The memory and the switch fabric have a system clock domain. The core clock domain for each of the port logic modules is different from the system clock domain.

Abstract: Aspects relate to power management for a peripheral component interconnect. Transmit traffic activity may be monitored for a peripheral component interconnect express (PCIe) link. Receive traffic activity may also be monitored for the link A first power of transmit lines of the link is managed as a transmit group in accordance with the transmit traffic activity. A second power of the receive lines of the link are managed as a receive group in accordance with the receive traffic activity. The first power of the transmit lines is managed independently of the second power of the receive lines.

Abstract: A method includes detecting a voltage at a configuration terminal of a mobile industry processor interface (MIPI) radio frequency front end (RFFE) device with a timing based on a MIPI RFFE signal received by the MIPI RFFE device, and setting an address for the MIPI RFFE device based on the detected voltage.

Abstract: There are provided a flat plate; a substrate having a first side and a second side facing an inner surface of the flat plate; a first receptacle connector that is provided along the first side of the substrate and configured to be coupled to a first plug of a first cable via a first opening of the flat plate; and a second receptacle connector that is provided along the second side of the substrate and configured to be coupled to a second plug of a second cable via a second opening of the flat plate, a distance from the inner surface to the first side is shorter than a distance from the inner surface to the second side.

Abstract: A system and method for evaluation, detection, conditioning, and treatment of neurological functioning and conditions which uses data obtained while a person is engaged in simultaneously in a range of primary physical tasks combined with defined types of secondary activity, such as listening, reading, speaking, mathematics, logic puzzles, navigation of a virtual environment, recall of past stimuli, etc. The data from the physical and secondary activities are combined to generate a composite functioning score visualization indicating the relative functioning of areas aspects of neurological functioning; including those in which deficiencies may be present, which are early indicators of possible neurological conditions. Through algorithmic recommendations combined with expert and user input, a conditioning regimen targeting neurological aspects of interest paired with periodic testing allows the user to track their progress in these areas over time.

Abstract: The present disclosure includes a suturing device including: a fixed arm having a fixed jaw including a first grasping slot configured to receive a needle; a movable arm coupled to a movable jaw including a second grasping slot configured to receive the needle, the movable arm configured to pivot relative to the fixed arm to pivot the movable jaw relative to the fixed jaw until the needle is received in the first grasping slot and the second grasping slot; and a needle transfer mechanism configured to grasp the needle in the first grasping slot or the second grasping slot. In some aspects, the suturing device includes a safety member configured to control when the movable arm moves. The present disclosure includes a loading apparatus including a loading slot configured to receive a fixed jaw and a slider configured to move the needle towards into the fixed jaw.

Abstract: Methods, systems, and devices for providing computer implemented services using managed systems are disclosed. To provide the computer implemented services, the managed systems may need to operate in a predetermined manner conducive to, for example, execution of applications that provide the computer implemented services. Similarly, the managed system may need access to certain hardware resources (e.g., and also software resources such as drivers, firmware, etc.) to provide the desired computer implemented services. To improve the likelihood of the computer implemented services being provided, the managed devices may be managed using a subscription based model. The subscription model may utilize a highly accessible service to obtain information regarding desired capabilities (e.g., a subscription) of a managed system, and use the acquired information to automatically configure and manage the features and capabilities of the managed systems.

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

Abstract: Enhanced apparatuses, systems, and techniques for coupling network-linked peripheral devices into host computing devices is presented. A method includes, over a network interface of a host device, obtaining an indication of a peripheral device available for associating with the host device. Based on the indication, the method includes initiating instantiation of the peripheral device into a Peripheral Component Interconnect Express (PCIe) subsystem of the host device by at least emulating behavior of the peripheral device over the network interface as a PCIe peripheral device coupled locally to the host system.

Abstract: An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window.

Abstract: A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

Abstract: Embodiments included herein are directed towards a transmitter circuit. The circuit may include a most significant bit (“MSB”) main driver and a most significant bit boost driver operatively connected to the MSB main driver. The circuit may also include a least significant bit (“LSB”) main driver and a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel non-return-to-zero (“NRZ”) data inputs.

Abstract: The present subject matter provides improvements of endoscopic retrieving devices. In specific, the present subject matter provides a net element with an extra wide tail section. The present subject matter provides a new weaving pattern. The present subject matter provides a new shape of the loop. The present subject matter provides a net with a combination of net elements, such as combinations of different net geometries and/or different net materials. The present subject matter provides a new and inventive loop. The present subject matter provides an improved second end of the tubular member. The present subject matter provides a new and inventive arm.

Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.

Abstract: The data transmission circuit includes: at least two data transmission structures. Each data transmission structure includes a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal. Data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal. Data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal. Data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal. A control module receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate an output control signal corresponding to the input control signal.