Patents Examined by Phong H Dang
  • Patent number: 11003612
    Abstract: A processing subsystem/endpoint subsystem connection configuration system includes a plurality of processing subsystems and a multi-endpoint adapter device that provides a plurality of endpoint subsystems. A bus exchange switch device couples the plurality of processing subsystems to the plurality of endpoint subsystems, and a connection configuration engine is coupled to the multi-endpoint adapter device and the bus exchange switch device. The connection configuration engine receives a connection resource request that requests connection resources for a first processing subsystem that is included in the plurality of processing subsystems. Based on the connection resource request, the connection configuration engine causes at least one of the plurality of endpoint subsystems to perform a first connection resource change operation. The connection configuration engine then configures the bus exchange switch device to provide the connection resources for the first processing subsystem.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Yogesh Varma, Shyamkumar T. Iyer, William Price Dawkins, Mukund P. Khatri
  • Patent number: 10997113
    Abstract: In general, in one aspect, the invention relates to a method for managing pool device resources, the method including obtaining, by a distribution manager, a resource use request from a user application, wherein the user application and the distribution manager are operating on a pool device, identifying a peripheral component interconnect (PCI) bus device, wherein the PCI bus device is located on a second pool device and connected to a pool device resource on the second pool device, and initiating access to the PCI bus device using a virtual switch operating on the pool device.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: May 4, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Nicole Reineke, James Robert King, Robert Anthony Lincourt, Jr.
  • Patent number: 10983927
    Abstract: An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 20, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Tomoyuki Ono, Masaki Nudejima, Takayuki Hashimoto, Suguru Oue
  • Patent number: 10963418
    Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 30, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Thomas Obkircher, Guillaume Alexandre Blin, James Henry Ross, Bryan J. Roll
  • Patent number: 10956350
    Abstract: The application discloses an electronic device with a USB Type-C connector, which is able to be coupled to another electronic device. The electronic device includes a control unit, a switch unit and a charge conversion unit. The control unit outputs a first control signal according to a result of power supply handshaking between the electronic device and the other electronic device. The state of the first control signal determines whether the other electronic device supplies power to the electronic device. The switch unit is coupled to the control unit, and receives a supply voltage output by the other electronic device, and the switch unit determines whether to output the supply voltage according to the state of the first control signal. The charge conversion unit is coupled to the switch unit. The charge conversion unit converts the supply voltage into a target voltage to supply power to the electronic device.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 23, 2021
    Assignee: Pegatron Corporation
    Inventor: Chi-Yu Wu
  • Patent number: 10949372
    Abstract: A line replacement unit includes a terminal controller, and a plastic optical fiber serial interface module (POFSIM) coupled between the terminal controller and the data bus. The POFSIM is configured to transmit digital optical signals to the data bus based on electrical signals received from the terminal controller, and transmit electrical signals to the terminal controller based on digital optical signals received from the data bus.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 16, 2021
    Assignee: THE BOEING COMPANY
    Inventors: Eric Y. Chan, Henry B. Pang, Tuong Kien Truong
  • Patent number: 10942878
    Abstract: An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 9, 2021
    Assignee: Arm Limited
    Inventors: Sean James Salisbury, Chiranjeev Acharya, Eduard Vardanyan, Premkishore Shivakumar
  • Patent number: 10942887
    Abstract: A device includes a first input/output (I/O) port for communication with an external processor, a second I/O port for communication with a second device, and an interface adaptor supporting communication through the first and second I/O ports via a protocol having a plurality of layers, including an application layer, a physical layer, and a physical adaptor layer. The application layer processes information according to an application layer format and the physical adaptor layer processes information according to a physical adaptor layer format. The device receives from the external processor through the first I/O port a request in the application layer format that one or more communication conditions be set for a physical layer of the second device, converts the request from the application layer format to the physical adaptor layer format, and sends the converted request in the physical adaptor layer format to the second device through the second I/O port.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmin Lee, Sungho Seo, Hyuntae Park, Hwaseok Oh
  • Patent number: 10936529
    Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine a Peripheral Component Interconnect Express (PCIe) endpoint, associated with a PCIe destination endpoint identification, includes a field programmable gate array (FPGA); may access a partial configuration for the FPGA; may construct multiple packets that include the PCIe destination endpoint identification and respective portions of the partial configuration for the FPGA; and may provide the multiple packets to the PCIe endpoint. In one or more embodiments, the one or more systems, methods, and/or processes may further map at least a portion of the FPGA to a virtual machine. In one or more embodiments, the one or more systems, methods, and/or processes may further combine the portions of the partial configuration for the FPGA to reconstruct the partial configuration for the FPGA; and may further program the FPGA with the partial configuration for the FPGA.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 2, 2021
    Assignee: Dell Products L.P.
    Inventors: Shyamkumar Thiyagarajan Iyer, Timothy M. Lambert, Duk Moon Kim
  • Patent number: 10929320
    Abstract: A system and method for generating a control bifurcation signal in accordance with the Open Compute Project (OCP) Specification. An OCP device is provided that has a bifurcation function with an input to activate a bus bifurcation function. An input/output control circuit having an output coupled to a bifurcation control line coupled to the OCP device is provided. The input/output control circuit is operable to provide a bifurcation control signal to the OCP device over the bifurcation control line during an auxiliary power phase transition period of powering-on the OCP device.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: February 23, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Le-Sheng Chou, Sz-Chin Shih, Shuen-Hung Wang, Jui-Chi Huang
  • Patent number: 10929321
    Abstract: The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. A bus IF is constituted by a master having an initiative of communication and a slave that communicates with the master under the control of the master. Additionally, the slave is provided with a detection unit that, when detecting a change in level of a signal line representing a declaration of initiation or end of communication by the master, outputs a detection signal indicating that the change in level of the signal line representing a declaration of initiation or end of communication has been detected, and a false detection avoidance unit that invalidates output of the detection signal during a specific time slot set in advance. The present technology can be applied to, for example, a bus IF that performs communication in conformity with the I3C standard.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 23, 2021
    Assignee: Sony Corporation
    Inventor: Hideyuki Matsumoto
  • Patent number: 10929331
    Abstract: Examples described herein generally relate to a layered boundary interconnect in an integrated circuit (IC) and methods for operating such IC. In an example, an IC includes a programmable logic region, a plurality of input/output circuits, a plurality of hard block circuits, and a programmable native transmission network. The programmable native transmission network is connected to and between the plurality of input/output circuits and the plurality of hard block circuits. The plurality of hard block circuits is connected to and between the programmable native transmission network and the programmable logic region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10896113
    Abstract: A method for lighting a backplane lamp of multiple NVMe hard disks is provided. The method includes: transmitting a VPP address to the backplane in a cyclic manner by the controller, and analyzing the address transmitted by the controller by a programmable logic device of the backplane after a data stream transmitted by the controller is received; transmitting, by the controller, hard disk lamp lighting information of a corresponding disk position to the programmable logic device of the backplane, if a VPP address analyzed by the backplane is the same as the VPP address transmitted by the controller; and performing logical conversion on the hard disk lamp lighting information, to convert a serial data stream on the VPP signal wires into a parallel signal, lighting a backplane lamp at a corresponding port, and uploading information of a position of the hard disk to the controller.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 19, 2021
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Shichao Cheng
  • Patent number: 10860516
    Abstract: Subject matter disclosed herein may generally relate to docking systems, and more particularly, to docking systems for portable computing devices such as, for example, tablet computing devices. The docking system may include (1) an enclosure for the portable computing device and (2) a base, where the enclosure can be docked to the base. A communication channel can be established between the portable computing device and the base via the enclosure and an electrical connection that exists when the enclosure is docked with the base. Through the communication channel, data such as credential data can be passed from the portable computing device to the base. The base can control whether the enclosure is permitted to be undocked from the base based on this credential data.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 8, 2020
    Assignee: Mobile Tech, Inc.
    Inventor: Robert Logan Blaser
  • Patent number: 10859991
    Abstract: The present invention relates generally to a universal programmable voltage module that activates and deactivates an electrical component based on a programmed voltage or voltage change on a multiplexed input. The universal programmable voltage module may have input circuitry for conditioning the multiplex input for a processor configured to execute instructions from a computer-readable medium; at least one control switch; power conditioning circuitry receiving power from a battery; at least one visual indicator; and switched output circuitry. Methods of operating the universal voltage module in both a momentary and a latched mode are also provided.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 8, 2020
    Assignee: MOBILE ELECTRONICS INC.
    Inventor: Aaron Sanio
  • Patent number: 10853300
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Vivek Kozhikkottu, Shankar Ganesh Ramasubramanian, Kon-Woo Kwon, Dinesh Somasekhar
  • Patent number: 10817452
    Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, a plurality of slave devices electrically connected to the master device via the eSPI bus, and a first resistor. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. The first resistor is coupled between the alert handshake control line and a power supply. Each slave device obtains the number of slave devices according to a first voltage of the alert handshake control line.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 27, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chih-Hung Huang, Chun-Wei Chiu, Hao-Yang Chang
  • Patent number: 10810047
    Abstract: An information processing device includes a processor; and an offload circuit coupled to the processor via links, the offload circuit including: a first circuit that computes processes of applications, a second circuit that collects values indicating performance information of the links for flows corresponding to the processes of the applications and maximum values indicated in performance information and usable by the links, and a third circuit that determines a flow not satisfying requested performance information based on the values indicating the performance information of the links for the flows, selects a link to which the flow is to be allocated, based on the maximum values indicated in the performance information and usable by the links and values indicated in performance information and currently used by the links, and allocates the flow to the selected link.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 20, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Takashi Miyoshi
  • Patent number: 10788875
    Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 29, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Derwin W. Mattos, Anup Nayak
  • Patent number: 10782745
    Abstract: An operation method of an electronic system includes the following steps. When a first communication module of the electronic device receives a call signal, a controller of an electronic device detects whether an expansion device is electrically connected to the electronic device. Based on a result of the controller detecting whether the expansion device is electrically connected to the electronic device, it is determined whether the electronic system performs sound amplification with a first speaker of the electronic device or performs playing with a second speaker of the expansion device.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 22, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: I-Lung Chen, Yi-Hsuan Wu, Wang-Hung Yeh, Yi-Chang Wu, Yu-Fan Chuang, Yu-Wei Lai