Abstract: Disclosed is a many-bit, groupable, reconfigurable, multi-valued, electronic operator and its construction method. Each bit of the electronic operator is provided with n column calculators and one potential combiner. A data input line is connected to an input terminal of an A signal selector, and an output terminal of the A signal selector is connected to a work permitter. Another input terminal of the work permitter is connected to a reconfiguration latch, and an output terminal of the work permitter is further connected to an output validator. Another input terminal of the output validator is connected to a power supply Vcc, and an output terminal of the output validator is connected to an output generator. Another input terminal of the output generator is connected to a reconfiguration circuit, and an output terminal of the output generator is connected to the potential combiner.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: Embodiments of an N-channel serial peripheral interface are described, and N-channel serial communication links comprising the same. Also described are methods of communication using N-channel serial communication interfaces and links.

Abstract: An interface for an I3C slave. The interface allows I3C slaves to also be connected to a conventional I2C bus that includes an I2C master. For this purpose, an additional adaptation device is provided that adapts the signals of the I2C bus for an I3C slave.

Abstract: The present disclosure relates to the field of optical communications. A board is disclosed. The board includes a level adjustment circuit, a detection apparatus, and a control apparatus. The detection apparatus is configured to: when the detection apparatus is connected to an optical module, receive an indication signal output by an upstream optical signal detection pin; continuously detect a received first level signal and the received indication signal. If there is a second level signal, opposite to the first level signal, the detection apparatus notifies the control apparatus that the optical module is inserted. If there is no second level signal in the signal received within the preset duration, the detection apparatus notifies the control apparatus that the optical module is absent. This makes the optical module less dependent on the in-position pin, and decreases a quantity of pins of the optical module.

Abstract: A single-wire transmission method, a chip and a communication system are disclosed, wherein the single-wire transmission method comprises: receiving X sets of data to be transmitted, a trigger flag before each set of data to be transmitted and an end flag after each set of data to be transmitted through a single line, wherein X is a positive integer greater than 0, and each set of data to be transmitted is represented by the number of transition edges; confirming the trigger flag; counting the transition edge after confirming the trigger flag to obtain a number of the transition edges, performing a decoding process according to the number of the transition edges until the end flag is received, wherein the transition edges are recounted and the decoding process is re-performed after the end flag is received each time. The data transmission time is shorter, which improves the data transmission efficiency.

Abstract: An interface module for coupling data buses to first signal line ports, to which signal lines of at least one first data bus are connectable, and second signal line ports, to which signal lines of at least one second data bus are connectable, has at least one connecting device for making at least one connection between one of the first signal line ports and one of the second signal line ports. In this case, the first signal line port connected to the second signal line port is alternately connectable to at least one other second signal line port and/or the second signal line port connected to the first signal line port is alternately connectable to at least one other first signal line port. A related system has at least one such interface module and at least one apparatus that has the at least one first data bus and/or at the least one second data bus.

Abstract: A method for detecting a Direct Memory Access (DMA) address capability at high address values when testing PCIe devices is disclosed. The method includes enabling an input/output (I/O) memory management unit (IOMMU); remapping physical addresses to virtual addresses at a high end of an address range; adding a peripheral component interconnect express (PCIe) device; and mapping physical memory addresses to high value memory addresses.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.

Abstract: A data processing apparatus may include a master device, a slave device, and a controller configured to arbitrate communication between the master device and the slave device by: setting a respective Time-out Counter (TC) for each of requests transmitted from the master device, allocating one or more virtual channels to each of one or more request groups, the one or more virtual channels respectively corresponding to priority levels, associating a request with a virtual channel corresponding to the priority level of the request, for each request group, selecting one of the leading requests of the respective virtual channels according to the TCs and transmitting the selected request to the slave device.

Abstract: A system and a method of interface communication being compatible with SFP+ optical modules and QSFP+ switch are provided. The system includes an adapter card. The adapter card includes a set of SFP+ golden fingers that comply with the SFP+ protocol, a set of QSFP+ golden fingers that comply with the QSFP+ protocol, and a microcontroller unit. The adapter card communicates with the SFP optical module through the SFP+ golden fingers, and communicates with the QSFP switch through the QSFP+ golden fingers. The microcontroller unit is used to extend and process the pin information in the adapter card, and to convert the two different protocols of SFP+ and QSFP+, so that the module under the SFP+ protocol can respond under the port of QSFP+, so as to realize the data communication between the SFP+ optical module and the QSFP+ switch.

Abstract: A bus system comprises a master, a first slave, a second slave, and a bus. The master is configured to be able to issue a second request to the second slave after issuing a first request to the first slave and before receiving a response to the first request. The bus comprises: a determination unit configured to, upon receiving the second request, determine whether to permit a transfer of the second request to the second slave; and a suspending unit configured to suspend the transfer of the second request to the second slave while it is determined by the determination unit that the transfer is not permitted. The determination unit determines whether or not the transfer is permitted based on a notification from the first slave regarding processing of the first request.

Abstract: The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

Abstract: A suture anchor for use in a knotless, suture-first technique for securing soft tissue to bone comprises a proximal anchor body and a distal tip having an eyelet configured to receive an end of a repair suture. Internal locking elements on the distal tip and the proximal anchor body are provided for locking the tip and anchor body together when the suture anchor is implanted in a bone. A suture assembly for use in an alternate knotless technique comprises a suture anchor, a repair suture, and a shuttle suture. Both the repair suture and the shuttle suture rea looped at one end and straight at the other end. In the alternate technique, the loop and tail of the repair suture are manipulated to form a luggage tag configuration extending around the tissue, and the shuttle suture is used to tightly secure the luggage tag configuration and tissue against the bone.

Abstract: Identifying a first controller and a second controller each connected to a computing device over a first serial bus for monitoring of the computing device; allocating, at the first controller, i) a first internal register bit of a first register indicating an arbitration status of the first controller with respect to the computing device and ii) a second internal register bit of the first register indicating an arbitration status of the second controller with respect to the computing device; allocating, at the second controller, i) a third internal register bit of a second register indicating the arbitration status of the first controller with respect to the computing device and ii) a fourth internal register bit of the second register indicating the arbitration status of the second controller with respect to the computing device.

Abstract: The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: Systems and methods for an interface with a widened interface-to-fabric shoreline between semiconductor circuits and a narrower interface-to-memory controller shoreline. The interface providing transitions from a first clock of a first circuit (e.g., field-programmable gate array (FPGA)), a second clock of a second circuit (e.g., high-bandwidth memory generation 2 (HBM2) stack, and a third clock of a physical layer of the second circuit. A first transfer between the first clock and the second clock may use a first set of first-in first-outs (FIFO) buffers, such as rate-matching FIFO buffers. A second transfer between the second clock and the third clock may use a second set of FIFO buffers, such as phase compensation FIFOs.

Abstract: An initiator emulator is implemented on a control plane of a switch fabric connected to target ports of a storage array having storage configured with logical partitions. After an initiator port of a server logs into the switch fabric and is blocked from discovering the target ports, the initiator emulator, acting as proxy for the initiator port, discovers information that indicates logical partition masking enforced at the target ports for the initiator port. The initiator emulator determines allowed (initiator (I), target (T)) (I, T) port combinations that should be allowed access via the switch fabric based on the information from the discovery. The initiator emulator configures the switch fabric with one or more zones based on the allowed (I, T) port combinations. The initiator emulator then sends to the initiator port an indication of a zone change to the switch fabric.