Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.

Abstract: The data transmission circuit includes: at least two data transmission structures. Each data transmission structure includes a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal. Data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal. Data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal. Data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal. A control module receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate an output control signal corresponding to the input control signal.

Abstract: A medical device comprises a control system, processing modules, and a wire bundle connecting the control system to the processing modules, the wire bundle comprising control lines and data lines. Each processing module is coupled to a respective set of sensors arranged to interface with a biological tissue site, the sensors being configured to capture analog physiological signals generated from the biological tissue site. The control system is configured to generate a control signal on the control lines to initiate a data collection cycle by the processing modules. In response to the control signal, each processing module is configured to perform a respective data collection process which comprises (i) capturing and processing an analog physiological signal on each enabled sensor to generate a data sample for each analog physiological signal captured on each enabled sensor, and (ii) outputting data samples to the control system on the data lines.

Abstract: In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. During an address assignment procedure, the master device assigns different respective dynamic addresses to the slave devices in order to address the slave devices for data communication; during the address assignment procedure, the slave devices are arranged in a daisy-chain configuration, wherein each slave device has a daisy-chain input and a daisy-chain output, the daisy-chain input of a slave device being coupled to the daisy-chain output of a previous slave device in the daisy chain configuration, the daisy-chain input of a first slave device being coupled to a daisy-chain enabling output of the master device; in particular, the master device is configured to assign the respective dynamic addresses to the slave devices based on their arrangement in the daisy-chain configuration.

Abstract: An I2C apparatus (100) comprising: a master device (102) and two slave devices connected through an I2C bus, whereby the two slave devices are programmed with the same default device address. A first slave device (108) is connected to the bus in a conventional configuration whereas a second slave device (110) is connected to the bus in a cross connected configuration such that a clock pin of the second slave is connected to the serial data line and the data pin of the second slave is connected to the serial clock line. In response to a detection that the data pin of the second slave is connected to the serial clock line, the second slave swaps the lines going from the clock and data pins to processing logic of the second slave; and modifies its default device address to ensure that each slave device has a unique device address.

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

Abstract: To enable preferable signal transmission between a plurality of daisy-chained devices at low cost. A transmission device generates a plurality of signals having different voltage levels and outputs the signals to a communication line at different timings. For example, the plurality of signals having different voltage levels is generated by a plurality of drivers or one driver. A receiving side can immediately determine whether or not it is information to be passed to the subsequent stage on the basis of only a difference in voltage level without logically analyzing contents of a signal, and cost of components such as a memory, verification cost, or the like are unnecessary so that the cost can be reduced.

Abstract: An interrupt request signal conversion system includes an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and a signal output terminal configured to send the one or more converted interrupt request signals to an interface module of a processor during operation. Each of the one or more converted interrupt request signals includes a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.

Abstract: A user space driver for input/output traffic distribution and packet processing is provided. A device can establish a driver in user space with access to a memory mapped region shared with a kernel of the device. The driver can access a packet stored to the memory mapped region by a network interface of the device responsive to receipt of the packet. The driver can provide the packet to a selected application of a plurality of applications for processing by the selected application.

Abstract: A port device for use in a USB extension environment that couples a host device to one or more USB devices is provided. The port device includes a USB physical layer interface configured to be coupled to a USB device, a host device, or a USB hub device; a remote interface configured to be coupled to an extension medium; and an endpoint table. The port device includes logic that, in response to execution by the port device, causes the port device to perform actions comprising: receiving a first USB message addressed to a first endpoint; in response to determining that the endpoint table indicates that the first endpoint is active, providing the first USB message for transmission to the first endpoint; and in response to determining that the endpoint table indicates that the first endpoint is inactive, providing a synthetic USB message for transmission to the host device.

Abstract: A peer-to-peer energy sharing network includes a common bus; a first node including a first local bus electrically connected to the common bus, at least one of a load, a storage device, and a generating capacity electrically connected to the first local bus through a first interface device, and a first local controller in communication with the first interface device; and a second node including a second local bus electrically connected to the common bus, at least one of a load, a storage device, and a generating capacity electrically connected to the second local bus through a second interface device, and a second local controller in communication with the second interface device, wherein the each interface device is controlled by its local controller to selectively pass electrical energy to and/or from the common bus via its local bus.

Abstract: Systems, apparatus, and methods that can elect a broker on a Message Queuing Telemetry Transport (MQTT) bus are disclosed. One system includes an MQTT bus and a set of client devices on the MQTT bus. Each client device maintains a set of attributes for each other client device and casts one or more votes for a particular client device on the MQTT bus to elect the particular client device as a new broker on the MQTT bus in response to a current broker on the MQTT bus becoming unavailable. The votes cast for the particular client device are based on a first value corresponding to one or more attributes for the particular client device relative to respective second values to the corresponding attribute(s) for each of the other client devices on the MQTT bus as calculated by each respective client device on the MQTT bus.

Abstract: A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.

Abstract: A signal receiver and an electronic apparatus including the same are disclosed. A signal receiver according to an embodiment of the present disclosure includes a first input interface to output a first type signal, second to fourth input interfaces to output the first type signal or the second type signal, a first buffer electrically connected to the first and the second input interfaces, a second buffer electrically connected to the second and the third input interfaces, a third buffer electrically connected to the third and the fourth input interfaces, and a fourth buffer electrically connected to the fourth and the second input interfaces. Accordingly, it is possible to simply implement a circuit for receiving a plurality of types of signals.

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

Abstract: Disclosed is a television including a display body and an interface extension apparatus. The display body includes a shell and a main board provided with a first interface and installed in the shell. The shell is provided with a channel opening. The interface extension apparatus includes a driving module and an interface extension line including a data line and a second interface. The data line is connected between the first interface and the second interface. The driving module is in transmission connection with the data line. The driving module is for driving one end of the interface extension line provided with the second interface to out of the shell through the channel opening, and driving the interface extension line out of the shell to be retracted into the shell through the channel opening. The application also discloses a television control method and a control apparatus.

Abstract: A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Abstract: A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.

Abstract: Method and apparatus for enhancing performance of a storage device, such as a solid-state drive (SSD). In some embodiments, the storage device monitors a rate at which client I/O access commands are received from a client to transfer data with a non-volatile memory (NVM) of the storage device. A ratio of background access commands to the client I/O access commands is adjusted to maintain completion rates of the client I/O access commands at a predetermined level. The background access commands transfer data internally with the NVM to prepare the storage device to service the client I/O access commands, and can include internal reads and writes to carry out garbage collection and metadata map updates. The ratio may be adjusted by identifying a workload type subjected to the storage device by the client.

Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.