Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: A disk drive is disclosed comprising a disk and a head actuated over the disk. The disk comprises a plurality of tracks, wherein each track comprises a plurality of data sectors including a parity sector, the parity sector comprising at least a P0 parity codeword and a P1 parity codeword. A plurality of data sectors are read from the disk (including the parity sector) to generate a plurality of data codewords CW0-CWn. The data sectors are decoded using an error correction code (ECC) decoder. When a single data codeword in CW0-CWn is unrecoverable using the ECC decoder, the single data codeword is recovered using the P0 parity codeword. When two data codewords in CW0-CWn are unrecoverable using the ECC decoder, the two data codewords are recovered using the P0 and P1 parity codewords.

Abstract: Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

Abstract: A method for storing redundant information in an array of data storage devices such that data is protected against two simultaneous storage device failures. The method assigns each data block to two different parity sets, each protected by a different parity block. The protected data blocks and the parity block each reside on a different data storage device.

Abstract: An encoder for encoding binary data bits supplied by a data source into pulse amplitude modulated multilevel symbols. The encoder includes a bit stuffer for receiving the data bits from the data source at a first data bit rate, which at most equals a maximum data bit rate. The bit stuffer then adds descriptive bits to the data bits at a descriptive bit rate, which at most equals a maximum descriptive bit rate. The encoder also includes a multilevel pulse amplitude modulator for receiving the data and descriptive bits from the bit stuffer and for converting the data and descriptive bits into pulse amplitude modulated multilevel symbols. When these multilevel PAM symbols are transmitted, they have a spectral energy characteristic which is below a predetermined low level threshold at a predetermined baseband bandwidth frequency. In addition, these multilevel PAM symbols have a symbol rate (i.e.

Abstract: A duplicate control and processing unit for telecommunications equipment consisting of two identical control units connected together is described. Each control unit (UC0, UC1) comprises a processing unit (UP0, UP1) which can be active or on standby, a peripheral data random access memory (RAM) for data processed during operation, and several peripheral circuits connected to the rest of the equipment. An EPROM (erasable programmable read-only memory) (CCL0, CCL1) in each processing unit contains the copy selection firmware. The data RAM and the peripheral circuits include a respective double gate access circuit (ACC0, ACC1) which allows selective access to the active processor only. The latter performs the writing cycles synchronously on both the duplicate data RAMs, allowing fast recovery of the operative synchronism by the standby processing unit, after switching due to failure of the active processing unit (FIG. 2).

Abstract: A digital phase adjustment circuit adjusts the phase between cell signals and a start-of-cell marker. The circuit relies on a known data pattern in unassigned cell signals in order to determine the phase. During a learning mode, the circuit samples an unassigned cell signal several times during a selected cell time to determine the location of the known data pattern. If the data pattern is not at the sampled position, the circuit increments the cell time during which it samples the next unassigned cell signal by one period, and decreases an amount of delay the circuit provides to a selected sample signal by one clock period. In this manner, the circuit can compensate for up to about two periods of delay before sampling the known data pattern. Thereafter, the circuit enters a tracking mode, and tracks phase variations between the cell signals and the start-of-cell marker. Additionally, the circuit selects a sample output signal which replicates the cell signals but is not subject to metastability.

Abstract: A system for determining a data stream using a variable length window for sampling of erred bits in the data stream is disclosed. A threshold maximum-allowable error rate is selected; a first window length to comprise a data stream sample is selected; the data stream is monitored for errors during the given window length; the allowable error is compared to the total number of errors detected during the monitoring step; and, if the detected error is greater than the allowable error, the window length is reduced and monitoring is continued using the reduced window length, else monitoring continues over successive window length periods. A signal degrade or signal fail condition signal is generated if the window length reaches zero. The system can be utilized to implement an automatic protection switching system for a SONET network.

Abstract: In a read operation in a read/write apparatus, an error process determination part determines whether or not an alternation process should be performed in a sector in which a read error has occurred. When it is determined that an alternation process should be performed, an address of a sector that is a target of the alternation process is stored in an automatic alternation address storage part. In a write operation, an automatic alternation process determination part determines whether or not a sector that is a target of the write operation has its address stored in the automatic alternation address storage part. When it is determined that the target address is stored, an automatic alternation process part performs an alternation process so as to allow a write process to be performed in an alternative area.

Abstract: An integrated CMOS circuit is disclosed for deinterleaving transmitted data packets. The circuit operates with a RAM buffer that is no larger than a block of interleaved data. An optimized addressing scheme is provided that minimizes on-chip hardware. The circuit provides an orderly initialization of the buffer, and a suitable emptying process during a channel change or other interruption of data flow.

Abstract: An error correction device for a digital video apparatus using a one-bit eraser signal is described. The error correction device includes an eraser occurrence counter for counting the eraser signal and generating a frequency signal of an eraser generated for each codeword of the received data, an eraser position detector for storing a position value in the codeword of the received data when the eraser signal is input and generating a position signal of the eraser generated for each codeword of the received data, and an error corrector for receiving the eraser frequency signal and the eraser position signal respectively from the eraser occurrence counter and the eraser position detector and correcting the eraser generated in the codeword of the received data, to thereby remarkably reduce the number of input pins in the decoder.

Abstract: A cyclic redundancy check (CRC) circuit for detecting and correcting errors in a data stream uses a decoder and a serial-to-parallel buffer to shorten arithmetic operation time. The CRC circuit includes a first gate for switching a serial input data stream into a syndrome register section, and a buffer register for converting the serial input data to a parallel data. The syndrome register section forms redundancies for input data stream. An OR gate receives data from the syndrome register section to enable a decoder if the syndrome register section detects an error in the data stream. The decoder decodes the output from the syndrome register section. The output of the decoder is exclusively-ORed with the input data in the parallel shift register. A latch circuit thereafter outputs a corrected serial data stream.

Abstract: A highly reliable computer system is intended to duplicate processors, compare the outputs of the processors with each other and enhance the validity of the output of processor system. If a mismatch between the outputs is detected, one of the processors performs a process of saving an internal state of the processor in amain memory and diagnosing factor of the detected mismatch. If the process is recognized to be continued in a duplex mode, the processors are re-synchronized by a processor reset, and initialize themselves and restore the internal information saved in the main memory for continuing the process having been proceeded before the fault occurred.

Abstract: A test circuit according to the present invention is so constructed that a memory has a data scramble function and a write pattern can freely be set and changed in a test mode. Each of data lines is a pair of complementary lines. A data scrambler and a data descrambler are arranged on the input and output sides, respectively. A latch circuit receives some of row addresses and supplies eight pairs of scramble signals CHNG to the data scrambler. An ENTRY/EXIT circuit outputs a TEST signal for selecting the normal and test modes. The latch circuit controls the modes in response to the TEST signal. In the test mode, the data, the data scrambler scrambles write data of the data lines in response to a scramble signal, and the data descrambler descrambles read data read out to the data lines from each memory cell in which the write data is stored, in response to the scramble signal, to return the data to the state prior to the scramble.

Abstract: A method and apparatus for reducing the number of I/O operations in a persistent storage system. A block of data to be written to a location on a persistent storage device is exclusive OR'd (XOR'd) with the block of data currently stored at the location on the device. The result of the XOR operation is examined for differences between the block of data currently stored in the location and the block of data to be written to the location. If the result of the XOR operation indicates that there is no difference between the block of data currently in the location and the block of data to be written to the location, additional I/O operations are avoided.

Abstract: A computer utility automatically monitors changes in configuration files stored on the computer hard disk. The recovery tool indicates to the user when changes are detected in the configuration files and provides the option to restore the configuration files to their state before they were changed if the computer system operates improperly. In addition, the recovery tool monitors selected application files for changes in the files or missing files, and prompts the user when a change is detected. The recovery tool also provides for monitoring of the CMOS memory which stores computer system operating functions and parameters. If possible corruption of the CMOS memory is detected, the recovery tool restores the contents of the CMOS to their proper state. Finally, the computer utility provides the option of making a bootable floppy diskette containing the computer system configuration.

Abstract: A control system for detecting a potentially faulty detector which may be causing faulty actuation of an actuator of a controlled system has an input-signal memory for storing the state of an input signal from the detector, an auxiliary input-signal memory for storing the state of an input signal provided by an auxiliary-signal generator, an arithmetic-logic unit for generating an output signal to be applied to the actuator in accordance with predetermined logic in conformity with the states of the input signals stored in the input-signal memory and auxiliary input-signal memory, and an output-signal memory for storing the state of an output signal generated by the arithmetic-logic unit. An identification code of an abnormal output signal corresponding to the abnormal actuator which is designated, and an input signal that has influenced a logical operation, performed by the arithmetic-logic unit, and which gave rise to the designated abnormal output signal, is extracted.

Abstract: In a method of generating a test sequence for testing a stuck-at fault supposed in a sequential circuit as a test circuit, the number of flip-flops which can be replaced with scan flip-flops among flip-flops included in the circuit under test is initially specified in the first step. Next, in the second step, there is calculated, for each of the flip-flops included in the circuit under test, the sequential depth of a clock defined as the minimum number of flip-flops that are passed through while the input side from the clock input terminal of the flip-flop is traced until an external input pin is reached. In the third step, flip-flops are identified with scan flip-flops by the number specified in the first step in the order of decreasing sequential depth of a clock, which was calculated in the second step.

Abstract: Apparatus and method for the early detection of faults in a head-disc assembly (HDA) from a disc drive manufacturing process. Parametrics are obtained from an HDA at a parametric station and provided to a pattern recognition system for estimating an error rate category from the measured HDA parametrics. The estimated error rate category and the parametrics are provided to a fuzzy inferencing system, which uses linguistic rules to classify the HDA as GOOD, MARGINAL or BAD, based upon the parametrics and the estimated error rate category. HDAs classified as GOOD or MARGINAL continue processing through dynamic burn-in (DBI), while HDAs classified as BAD are subjected to rework. The pattern recognition system includes a reference database containing historical parametric and associated error rate data, which is updated over time by the subsequent inclusion of selected parametrics and measured error rates for HDAs subjected to DBI.

Abstract: In order to prevent data corruption and inconsistency caused by incorrect assumption regarding a presumably failed node and/or program, a fail-fast timer mechanism enforces deadlines, i.e. enforces timeliness in programs. For example, given a program which needs to ensure a given code segment is executed within a specified deadline, the program arms a fail-fast timer before executing the code segment. After completing the execution of the code segment, the program disarms the fail-fast timer. If the program executes too slowly and the fail-fast timer expires before the fail-fast timer has been disarmed, the entire node is forced to stop very quickly (i.e. the node fails fast). The fail-fast timer of the present invention also triggers if the program exits before disarming a previously armed timeout.