Abstract: The software error handling determines the nature of the fault and takes different action depending upon the nature of the fault. If the fault prevents the data processing system from continued reliable operation, then the element causing the fault is immediately disabled. Otherwise, the element which is the source of the fault is treated so that it does no harm to the system and causes no further faults. The element can then be completely handled during normal software status checks.

Abstract: A portable semiconductor data storage device includes a data word storage circuit for storing data words, a redundant word storage circuit for storing redundant words relative to the data words, an error detection circuit for detecting an error bit in a data word stored in the data word storage circuit from the redundant word stored in the redundant word storage circuit, and an error correction circuit for correcting the erroneous bit detected by the error detection circuit.

Abstract: A method and device for detecting errors in a digital time switch that does not require the signal to be synchronous throughout a multi-plane processing unit in a digital time switch. The present invention allows for the detection and localization of errors occurring in one section of one plane in a multi-plane unit. The invention is preferably included in a telecommunications system operating with pulse code modulation and time multiplex. In a multi-plane portion of a digital time switch, there is generated for each one of corresponding parallel planes at corresponding locations a compressed version of the data signal and the corresponding compressed data signals are compared. An alarm is given when the comparison shows a difference between the compressed signals.

Abstract: By selectively associating output signal lines with logic circuit input signal lines, it is possible to produce a combination logic circuit and latch string in which no pair of adjacent latches is connected to the same cone of logic in the logic circuit. This provides greatly improved capabilities for delay or AC circuit test with respect to the independence of test pairs of excitation data. The objective may also be achieved in whole or in part through the use of dummy latch elements which do not feed any logic circuit input signal lines.

Abstract: A scan operation executing system includes a command decoding unit and a scan mode setting unit. The command decoding unit is initialized together with a diagnostic control unit in accordance with a diagnostic activation signal from a diagnostic processor, outputs a reset signal in response to a diagnostic command for a scan operation execution request subsequent to the diagnostic activation signal, and outputs a reset signal in response to a diagnostic command for a scan mode reset request. The scan mode setting unit is set by a set signal from the command decoding unit to supply a scan mode signal to a processing unit of a main processor and is reset by the reset signal to disconnect the scan mode signal.

Abstract: A built-in self test (BIST) circuit verifies the operation of a circuit under test in an integrated circuit. The BIST generates a series of test vectors with linear feedback shift register (LFSR) and applies the test vectors to the circuit under test. The output signal from the circuit under test in response to the test vectors is routed back and accumulating in a predetermined manner in the LFSR for providing a test signature. Thus, the same components in the LFSR generating the test vector also perform the accumulation of the test signature. The accumulating test signature may be used as a subsequent test vector.

Abstract: RAM Built-In Self-Test logic is presented that utilizes a linear feedback shift register (LFSR) to generate data. Preferably, an LFSR is also utilized for address generation during memory self-testing. More than one cycle is implemented with offset of successive data sequences relative to address sequences to increase fault coverage. Memory storage is utilized in the data generation to enable a reduced area of the data generation circuitry.

Abstract: In a sampled data transmitting apparatus in which the sampled data to be transmitted are divided into odd-numbered samples and even-numbered samples and arranged in different rows of a two-dimensional data array, and in which error correction codes are annexed to each row and to each column of the two-dimensional data array, the row arraying sequence in one of the odd-numbered or even-numbered rows is caused to differ from the row arraying sequence in the other of the odd-numbered or even-numbered rows so that odd-numbered data and even-numbered data continuous with the odd-numbered data are not arranged in one row. In this manner, even when error correction becomes impossible by the error correcting code for one row, interpolation remains feasible because there exist no odd-numbered data or even-numbered data contiguous to each other in the row.

Abstract: An array disk apparatus capable of identifying locations where data reconstruction has failed. The apparatus comprises a disk controller containing a data reconstructing unit, a "reconstruction unsuccessful" information generating unit and a "reconstruction unsuccessful" information storing unit. The data reconstructing unit reconstructs lost data based on the data from the magnetic disk units other than the failed and repaired unit and on parity data associated with the data. The "reconstruction unsuccessful" information generating unit generates "reconstruction unsuccessful" information if another magnetic disk unit develops a read error during a data reconstruction process. The "reconstruction unsuccessful" data storing unit stores the "reconstruction unsuccessful" information to the failed magnetic disk unit after the repair thereof.

Abstract: A central processing unit arrangement for detecting a fault in a central processing unit system that includes a master processor and a slave processor. Master and slave processors are resynchronized at every bus cycle by conditioning the processors' READY signal with the ADS (address status) signals from each processor (ADS indicates that an access cycle has begun and a valid address is present on the address bus). This method of synchronization was selected over the more traditional method of lock-step, which was deemed impractical to implement given the timing constraints of a high speed bus. Also, the dual processors may not always begin their respective bus cycles on the same clock. In addition, it is necessary to synchronize processors for the first instruction fetch following a reset, because the time of completion of an internal self-test may not be deterministic.

Abstract: The system of the present invention has a plurality of sensors 1a, 1b and 1c and a system control circuit which includes a case memory portion and a work script memory portion. In response to application of state data from the sensors 1a, 1b and 1c, the system converts the state data into symbolic data. Then the symbolic data is evaluated to judge whether or not a fault exists and to specify a fault symptom. As a result of the judgement, a fault symptom and a fault in the objective machine are determined. Thereafter, cases stored in the case memory portion are retrieved on the basis of the results of the fault diagnosis and a fault simulation. A case which closely resembles the present state of the objective machine is selected. Then, repair work described in the selected case is executed.

Abstract: A convolutional decoder for decoding a received message of digital data convolutionally encoded at a constraint length of K, comprises branch metric calculating circuitry for receiving the data and providing output signals indicative of the branch metrics therefor, a plurality of 2.sup.K-1 circuits for receiving the output signals and computing state metrics, the circuits being interconnected to form a trellis and generating decision bits and a plurality of 2.sup.K-1 memory circuits, the memory circuits being interconnected also to form a trellis and responsive to the decision bits to output a decoded digit of the received message data.

Abstract: An error-bit generating circuit for use in a nonvolatile semiconductor memory device, particularly in an EEPROM. The circuit is capable of easily checking the deterioration of operational performance in an error checking correction device thereof, by intentionally writing bit-error data into a memory cell thereof. The error-bit generating circuit includes a parity generator for generating specified bits of parity data according to input data received from an input buffer, means for writing into a memory cell array the input data and parity data, means for, after reading out the input data and parity data from the memory cell array, correcting an error-bit among the input data and then providing the corrected data, and an error-bit generator coupled between the input buffer and the memory cell array, for generating an error-bit signal onto a selected bit of the input data in response to a control signal and an address signal.

Abstract: A system includes an image forming apparatus or copier, and a central controller for remotely determining a cause of malfunction of the copier. The copier includes a control unit including a self-diagnostic portion; a selection portion for setting the control unit to a self-diagnosis mode; and a communication device for, when the self-diagnosis mode is set, connecting the control unit with a communication line. The self-diagnostic portion includes a receiving section for receiving diagnostic information through the communication device; a diagnostic section for executing self-diagnosis against the copier, on the basis of the received diagnostic information; and a transmitting section for transmitting the results of the self-diagnosis through the communication device.

Abstract: A method for identifying a signal subject to intersymbol interference comprising the steps of receiving .tau.+1 samples of the signal where .tau. is greater than or equal to one; searching a tree representation of known values to determine the path of the branch of the tree which most closely corresponds to the .tau.+1 samples of the signal; and releasing the symbol of the first metric of the determined branch. The released symbol is the identity of the sample. Preferably, the receiving step includes the step of receiving .tau.+1 sequential samples, with each sample corresponding to a unique portion of the signal, and the searching step includes the step of comparing each symbol of each metric of each path of each branch with the symbol's corresponding sample in regard to time.

Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW.

Abstract: A phase synchronization pull-in system used in a bit error detecting apparatus includes a monitored circuit for inputting an input signal and processing the input signal when an operation of the monitored circuit is to be monitored, a standard circuit for processing an output of the monitored circuit inversely to the processing in the monitored circuit, a phase synchronization circuit for inputting the input signal of the monitored circuit and adjusting a first delay time of the input signal so that the first delay time coincides with a second delay time of the output of the standard circuit corresponding to the input signal, a bit error detecting circuit for detecting a difference between the input signal, after being delayed through a variable delay circuit, and the output of the standard circuit, bit by bit, and a controller for controlling the adjusting of the first delay time, a monitoring operation, and a phase synchronization pull-in operation.

Abstract: A method is disclosed for generating a control signal (TMS) which may be used to control the test activity of boundary scan system (10). The method is initiated by loading a multi-bit control macro (STI, DTI or DSTI) into a register (38) whose output is coupled back to its input. After loading of the macro, its identity is ascertained by a macro controller (42) which serves to decode a multi-bit signal (IT) whose state is indicative of the macro type. The macro controller (42) actuates the register to shift out the bits of the control macro in a sequence dependent on the macro's identity in order to generate the appropriate control signal. As each bit is shifted out, it is shifted back into the register so as to allow the same sequence of bits to be repeatedly shifted out.