Abstract: A circuit device in which a processing load of a processing device with respect to error detection performed on image data can be reduced, and an electro-optical device, an electronic apparatus, a mobile body, an error detection method and the like. The circuit device includes: an interface unit that receives image data; and an error detection unit that performs error detection. The interface unit receives the image data including display image data and error detection data that includes at least position information regarding an error detection region, and the error detection unit performs the error detection on the display image data based on the display image data of the error detection region that is specified by the position information.

Abstract: A method for checking a signal transmission of a specified message with a number of d bits from a sender to a receiver by a control unit using a linear block code generated via a coding tool, a channel model, and a specified linear feedback shift register, which is parameterized via a generator polynomial, wherein the residual error probability of different Markov-modulated Bernoulli processes is calculated, where boundary conditions for signal transmission can be specified by using a characterizing Markov-modulated Bernoulli process and also a linear feedback shift register, where integration of the calculation of the residual error probability is performed in a dynamic, intelligent control circuit such that the respective residual error probabilities can be determined for different generator polynomials.

Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

Abstract: In one example a computer implemented method comprises generating an error correction code for a memory line, the memory line comprising a first plurality of data blocks, wherein the error correction code comprises a first plurality of parity bits and a second plurality of parity bits, applying a domain-specific function to the second plurality of parity bits to generate a modified block of parity bits, generating a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least a portion of the modified block of parity bits, encoding the first plurality of data blocks and the metadata block to generate a first encoded data set, and providing the encoded data set and the encoded metadata block for storage on a memory module. Other examples may be described.

Abstract: A resource upgrade predictor can be operable to receive, from a first network node device, traffic information. Based on the traffic information, the resource upgrade predictor can obtain network utilization data related to other network node devices having a similar interference characteristic (e.g., signal-to-noise ratio) to the first network node device. The resource upgrade predictor can use this network utilization data to determine a demand (e.g., demand level, demand point) at which at least a defined value related to a transmission link capacity associated with transmissions between the first network node device and the user equipment, is attained (e.g., a percentage of physical resource block loading).

Abstract: Methods and apparatus for Exclusive OR (XOR) programming of a memory device are described. A program internal to a device calculates parity or other values using an XOR Program Rule. In some embodiments, the program generates and stores a parity result directly in the memory device itself without intervention by an external controller. A method of parity generation in a memory device comprises executing an internal self-accumulating parity program, wherein the program accumulates a parity sum by superimposing newly accumulated parity information over previously stored parity information in the auxiliary memory system. In a stand-alone device embodiment, a new command “XOR program” is received with address and input data parameters causing stored data to be read at the input address and an XOR operation of the read data and new input data is performed. The results of the computation are written into memory.

Abstract: A method and apparatus for memory built-in self-test (MBIST) may be configured to load a testing program from an MBIST controller, execute the testing program, and determine and write pass/fail results to a read-out register. For example, in various embodiments, the testing program may comprise one or more write operations that are configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted in order to test stability associated with a memory bitcell, create DC and AC noise due to byte enable mode stress, check at-speed byte enable mode timing, and execute a self-checking algorithm that may be designed to verify whether data is received at a data input (Din) pin. Any memory bitcells storing a value different from an expected value after performing the write operation(s) may be identified as having failed the MBIST.

Abstract: In order to enable to estimate whether the bit error occurs steadily or instantaneously, an error monitoring method according to an exemplary aspect of the invention includes: detecting number of error bits of received data per bits whose number is predetermined, comparing the number of error bits with a threshold value which is predetermined, and counting and outputting number of times of continuous occurrence of the comparison result's indicating being large, and number of times of continuous occurrence of the comparison result's indicating being small.

Abstract: A digital system includes nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of transferring read data and write data relating to the memory, can be changed on a codeword-to-codeword basis based on input parameters.

Abstract: Embodiments described herein relate to testing the integrity of a storage system's metadata while corresponding structured data remains online. Embodiments also relate to enabling corrupt storage system metadata to be repaired while the metadata remains in use and while its structured data remains online. Corruption detection and repair is described with respect to allocation metadata and reference count metadata. The embodiments are applicable to many types of storage systems, including file systems and databases, for example.

Abstract: A method of performing error recovery of encrypted data frames is disclosed. A data packet is received, and a decryption operation is performed on the data packet. The data packet is compared with one or more data packets stored in a recovery buffer to identify a duplicate of the data packet when the decryption operation fails. One or more bits affected by one or more bit errors are identified based on a comparison between the data packet and the duplicate of the data packet. Different combinations of bit values for the one or more bits are determined. The decryption operation is performed on the data packet with the different combinations to identify a correct combination of bit values for the one or more bits. The data packet is recovered (e.g., corrected so that it can be decrypted and consumed) based on the correct combination of bit values.

Abstract: Technology is described herein for a generalized low-density parity-check (GLDPC) decoder. A GLDPC decoder comprises an LDPC decoder and a syndrome decoder. The LDPC decoder is configured to generate a codeword for encoded data. The syndrome decoder is configured to decode a syndrome of punctured check nodes based on a linear block code having more than one information bit. The GLDPC decoder is configured to control the LDPC decoder to compute an initial value of the syndrome of the punctured check nodes based on an initial estimate of the codeword from the LDPC decoder. The GLDPC decoder is configured to alternate between controlling the syndrome decoder to correct the syndrome and controlling the LDPC decoder to update the codeword based on the corrected syndrome. The GLDPC decoder is configured to provide a decoded version of the encoded data based on a final estimate of the codeword.

Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.

Abstract: An encoding method changes an encoding rate of an erasure correcting code. One cycle is defined as 12k bits (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of 1/2, and includes information and parity. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k?1) X6(i+k?1)+1, X6(i+k?1)+2, X6(i+k?1)+3, X6(i+k?1)+4, and X6(i+k?1)+5. Known information is inserted in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information.

Abstract: A system includes a plurality of memory cells. Each memory cell is programmed to a data state corresponding to one of multiple cell programmed voltages. The memory cells are read to determine a programmed data state of each memory cell. Error correction decoding is performed to determine a corrected data state of each memory cell. The corresponding cell levels, or programmed voltages, are determined based on the programmed data state and the corrected data state. A first error count represents a total number of error cells that have a higher cell level for the corrected data state than the programmed data state. A second error count represents a total number of error cells that have a lower cell level for the corrected data state than the programmed data state. The system is configured to perform a memory operation based on the first error count and the second error count.

Abstract: A method and apparatus for receiving a Scheduling Assignment (SA) by a User Equipment (UE) in a communication system in which a base station transmits the SA including at least one Information Element (IE) are described. The method includes receiving the SA; identifying if a first IE included in the received SA is set with a first predetermined value and at least one bit in a second IE included in the received SA is set with a second predetermined value; and performing an action corresponding to a semi-persistent scheduling, if the first IE included in the received SA is set with the first predetermined value and the at least one bit in the second IE included in the received SA is set with the second predetermined value.

Abstract: The present invention relates to transmitting data on a shared communication channel in a communication system supporting multiple hybrid automatic repeat request processes and configurable to apply a bundling of transmission time intervals. The data transmitting including mapping of TTIs of the HARQ processes cyclically onto subframes. In order to efficiently support dynamic bundle scheduling, when a grant is received during a bundle transmission, this grant becomes a shifting grant, according to which the bundle is transmitted and according to the location of which the timing of the grant reception and the data transmission is adapted. The transmission of the shifted bundle is performed in accordance with the state of its retransmission process, i.e. the bundle is either initially transmitted or retransmitted.

Abstract: Methods and systems for decoding monitored communication signals using previously identified side information. Information, which is used for decoding a given frame and is provided to the decoder not via the main communication channel between a base station and a mobile station, is referred to herein as “side information.” The side information can also be viewed as extrinsic information that was derived during previous decoding operations. The monitoring system holds, for certain frames, a-priori information of one or more data values that are expected in these frames. Decoding using this a-priori information enables an Error Correcting Code decoder to successfully decode such frames, which would otherwise fail to decode.

Abstract: A control information transmission method, a base station, and user equipment are disclosed. The transmission method includes: sending, by a base station, first control information on a second carrier, where the first control information is used by the base station to send data on a first carrier according to the first control information; and sending, by the base station, the data on the first carrier according to the first control information; where duration of a transmission time interval of the first carrier is less than duration of a transmission time interval of the second carrier.

Abstract: A method for execution by a computing device of a dispersed storage network includes dispersed storage error encoding a data segment to produce a set of encoded data slices. Storage of more than a write threshold number of encoded data slices of the set of encoded data slices in a set of storage units is facilitated. A plurality of favorably stored encoded data slices is identified. A number of stored encoded data slices for deletion is determined, and the number of stored encoded data slices for deletion is selected from the plurality of favorably stored encoded data slices. Deletion of the selected number of stored encoded data slices for deletion is facilitated.