Abstract: A computing system comprises a host system, a first storage device, a second storage device, a third storage device, a fabric interconnect device and a controller separate from the host system. The first, second, and third storage devices comprise a first, second, and third local memory buffer. The fabric interconnect device is configured to connect the first, second, and third storage devices over a fabric network to the host system. In response to receiving a write operation from the host system, a controller (e.g., on the first storage device or the fabric interconnect device) is configured to calculate error-correction data (e.g., parity data) by using data-protection operations (e.g., XOR operation(s)) directly on data stored on the first, second, and third local memory buffer, without having to rely on computing resources of the host system.

Abstract: Fast parallel CRC determination to support SSD testing includes a test data pattern generator for generating test data for storage onto a memory storage device under test (DUT), wherein the generator is operable to generate, every clock cycle, a respective N bit word comprising a plurality of M bit subwords, a digest circuit operable to employ a digest function on each N bit word to produce, every clock cycle, a respective word digest for each N bit word, and a storage circuit operable to store each N bit word along with an associated word digest to the DUT.

Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: Techniques are described for wireless communication. One method includes identifying a set of punctured bit locations in a received codeword. The received codeword is encoded using a polar code. The method also includes identifying a set of information bit locations of the polar code, with the set of information bit locations being determined based at least in part on polarization weights per polarized bit-channel of a polar code decoder that are a function of nulled repetition operations per polarization stage of the polar code identified based at least in part on the set of punctured bit locations. The method further includes processing the received codeword using the polar code decoder to obtain an information bit vector at the set of information bit locations.

Abstract: A nonvolatile memory device includes a memory cell array; a peripheral circuit configured to perform an operation corresponding to a command provided from an external device, for the memory cell array; a fail occurrence register configured to store fail occurrence information for intentionally causing an operation fail to occur; and a control logic configured to store the fail occurrence information in the fail occurrence register based on a fail occurrence command received from the external device, control the peripheral circuit to perform a test operation corresponding to a test operation command received from the external device, for the memory cell array, and control the peripheral circuit to cause an intentional fail to occur in the test operation, based on the fail occurrence information.

Abstract: A memory device includes first, second, third, and fourth memory cell groups and first and second transmitters. The first and second memory cell groups share first local lines. The third and fourth memory cell groups share second local lines. The first transmitter transmits first data to first global lines based on a read command. The first data is output from one of the first memory cell group and the second memory cell group on the first local lines. The second transmitter transmits second data to second global lines based on the read command. The second data is output from one of the third memory cell group and the fourth memory cell group on the second local lines. The number of the first global lines is different from the number of the second global lines.

Abstract: According to one embodiment, a memory device, includes a first memory cell, and a second memory cell adjacent to the first memory cell; and a sequencer configured to, when data is read from the first memory cell: perform a first read operation on the second memory cell; perform a second read operation on the first memory cell; perform a third read operation on the first memory cell by applying a voltage different from that applied in the second read operation to a gate of the second memory cell; and generate first data stored in the first memory cell and second data for correcting the first data, based on results of the first to third read operations.

Abstract: An error mechanism provides stored error information to assist in determining the cause of failure of a storage device such as a hard disk drive. The error mechanism gathers information surrounding an error event from various software and hardware components in the system. An event command is sent to the storage device that includes the gathered information. The storage device stores the gathered information from the event command in a log on the storage device. After the storage device is removed from the system the error information in the log can be used to determine the cause of the failure. The event command may be standardized into an existing industry communication protocol or be vendor specific.

Abstract: Low-density parity check (LDPC) decoder circuitry is configured to decode an input codeword using a plurality of circulant matrices of a parity check matrix for an LDPC code. Multiple memory banks are configured to store elements of the input codeword. A memory circuit is configured for storage of an instruction sequence. Each instruction describes for one of the circulant matrices, a corresponding layer and column of the parity check matrix and a rotation. Each instruction includes packing factor bits having a value indicative of a number of instructions of the instruction sequence to be assembled in a bundle of instructions. A bundler circuit is configured to assemble the number of instructions from the memory circuit in a bundle. The bundler circuit specifies one or more no-operation codes (NOPs) in the bundle in response to the value of the packing factor bits and provides the bundle to the decoder circuitry.

Abstract: This application provides a data sending method, a data receiving method, a sending device, and a receiving device. The data sending method includes: sending a 1st polar-coded code word, where the 1st code word includes n 1st information bits carrying user data; and sending a 2nd polar-coded code word after sending the 1st code word is completed, where the 2nd code word includes p 2nd information bits carrying user data, and each 2nd information bit carries same user data as one uniquely corresponding 1st retransmission bit. According to the data sending method, the data receiving method, an apparatus, a device, and a system provided in this application, decoding performance of the code words can be improved.

Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.

Abstract: Provided herein may be an error correction circuit. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a NB-LDPC code may include a symbol configuration circuit for configuring an initial symbol to be assigned as a variable node value to a variable node, a reliability value initialization circuit for initializing first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node, and a symbol correction circuit updating the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and adjusting the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value.

Abstract: A communications device acting as a relay device configured to communicate with an infrastructure equipment of a mobile communications network and a receiving communications device operating with the mobile communications network. The communications device acting as the relay device comprises receives signals representing protocol data units formed from one or more service data units via a first wireless access interface from the infrastructure equipment according to a first automatic repeat request protocol for transmission to the receiving communications device, transmits signals representing the received protocol data units via a second wireless access interface to the receiving communications device according to a second automatic repeat request protocol, and stores, in a buffer, the protocol data units received from the infrastructure equipment according to the first automatic repeat request protocol.

Abstract: Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when writing data to a superblock of the memory, a wordline of the superblock stores “D+P” parity bits that protect “D” data bits of a codeword having a length of “2D+P.” Other wordlines of the superblock store codewords each having a length of “D+P” (e.g., “D” data bits and “P” parity bits). If the decoding of any of these codewords of length “D+P” fails, the “D+P” parity bits are used to re-decode the failed wordline.

Abstract: Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.

Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.

Abstract: Digital testing is performed on an integrated circuit while radiation upsets are induced at locations of the integrated circuit. For each digital test, a determination is made as to whether there is a variation in the output of the digital test from an expected output of the digital test. If there is variation, a time of the variation is indicated. In one example, a location of a defect in the digital circuit can be determined from the times of the variations. In other embodiments, a mapping of the digital circuit can be made from the times.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: A test interface board includes a first input terminal, a second input terminal, an output terminal, and a transmission line. The first input terminal receives a first test signal for testing a semiconductor device. The second input terminal receives a second test signal for testing the semiconductor device. The output terminal outputs the first test signal and the second test signal to the semiconductor device. The transmission line electrically connects the first input terminal, the second input terminal, and the output terminal such that the first test signal and the second test signal are merged.