Abstract: A memory controller is provided to include an error correction encoder and an error correction decoder. The error correction encoder is configured to encode a message at a second code rate and generate a codeword including a message part, a first parity part, and a second parity part. The error correction decoder is in communication with the error correction encoder and configured to perform at least one of i) first error correction decoding operation at a first code rate greater than the second code rate based on a first parity check matrix and first read values or ii) second error correction decoding operation at the second code rate based on a second parity check matrix and second read values. The first read values correspond to a partial codeword including the message part and the first parity part, and the second read values correspond to an entire codeword.

Abstract: Methods, systems, and apparatus for EM communications. One of the methods includes determining, at a first device, that a second device is present; initiating a half duplex communication with the second device; configuring communication with the second device including determining whether full duplex communication is available; in response to a determination that full duplex communication is not available, communicating with the second device in half duplex mode; and in response to a determination that full duplex communication is available, communication with the second device in full duplex mode.

Abstract: A computer-implemented method includes encoding an array of (p?1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r?1, and k?p. The method includes each column in the p×(k+r) array has an even parity and symbol i in column r+j, for 0?i?p?1 and 0?j?r?1, is the XOR of symbols in a line of slope j taken with a toroidal topology modulo p in the k columns starting in symbol i of column 0.

Abstract: Systems and methods are provided for fast cyclic redundancy check code generation. For example, a method includes representing the sequence of bits as a polynomial over a Galois field base 2; partitioning the polynomial into a plurality of partial polynomials, wherein the polynomial equals the sum of the partial polynomials; concurrently generating a respective partial CRC code for each of the partial polynomials; weighting each partial CRC code according to a position of the respective partial polynomial in the polynomial; and summing the weighted partial CRC codes.

Abstract: In described examples, data are stored in a destructive read non-volatile memory (DRNVM). The DRNVM includes an array of DRNVM cells organized as rows of data. The rows of data are subdivided into columns of code word symbols. Each column of code word symbols is encoded to store an error correction code symbol for each column of code word symbols.

Abstract: Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has interfaces between the logic device and memory device that cannot be directly accessed at a package ball. Test programs are concurrently executed by the logic device and the memory device to reduce testing time. Each memory device includes a BIST (built-in self-test) module that is initialized and executes the memory test program while the one or more modules within the logic device are tested.

Abstract: A technique for hybrid automatic repeat request (HARD) transmissions using low-density parity-check (LDPC) coding with self-decodable retransmissions is disclosed. Data is encoded using a low-density parity check code to obtain encoded data, where the encoded data includes core data and non-core data. The encoded data is then stored in a buffer for transmission. A plurality of redundancy versions of the encoded data is then transmitted, wherein all redundancy versions of encoded data include core data, and each of the transmitted redundancy versions of the encoded data includes at least a different subset of the core data. The core data may be reordered prior to obtaining at least one of the different subsets of core data. Each of the transmitted redundancy versions of the encoded data includes sufficient core data to permit self-decodability of the transmission at a receiver.

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

Abstract: A method for operating a memory system which includes a memory device and a controller for controlling the memory device, the operating method includes searching one or more open memory blocks included in the memory device, when a booting operation is performed; detecting one or more erase pages included in each of the open memory blocks; checking an erase threshold voltage distribution corresponding to each of the erase pages; counting a number of first bad pages among the erased pages based on the erase threshold voltage distribution; and switching a first open memory block including the first bad pages among the open memory blocks into a first closed memory block when the number of first bad pages is equal to or greater than a first threshold value.

Abstract: A memory controller is provided. The memory controller is coupled to a flash memory that includes a plurality of physical blocks, and each physical block includes a plurality of physical pages, and some of the physical pages are defective physical pages. The memory controller includes a processor that is configured to set a total target initialization time for an initialization process of the flash memory. The processor sequentially selects a current physical block from among all the physical blocks to perform the initialization process, and it performs a read operation of the initialization process on the current physical block using a read-operation threshold. In response to the read operation of the current physical block being completed, the processor dynamically adjusts the read-operation threshold of the read operation of the physical blocks, so that the initialization process is completed within the total target initialization time.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time (“TAT”), test data volume, tester memory and cost associated with design for test (“DFT”), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

Abstract: The invention relates to an improved transmission protocol for uplink data packet transmission in a communication system. A receiver of a user equipment receives a Fast Retransmission Indicator, referred to as FRI. The FRI indicates whether or not a base station requests a retransmission of a previously transmitted data packet. A transmitter of the user equipment retransmits the data packet using the same redundancy version as already used for the previous transmission of the data packet.

Abstract: Devices and techniques for NAND device mixed parity management are described herein. A first portion of data that corresponds to a first data segment and a second data segment—respectively defined with respect to a structure of a NAND device—are received. A parity value using the first portion of data and the second portion of data is computed and then stored for error correction operations.

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

Abstract: Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

Abstract: The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.

Abstract: A memory array with a fabrication joint includes a controller configured to apply a detection voltage on a word line coupled to a plurality of bitlines, count a number of bitlines having a first type of response to the detection voltage, and on condition that the number of bitlines exceeds a configured value, program memory cells on at least one dummy word line adjacent to the fabrication joint with a particular threshold voltage.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.

Abstract: A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data.