Patents Examined by Pierre-Michel Bataille
  • Patent number: 10042585
    Abstract: A method is described that includes generating, by a controller of a storage device, operating statistics associated with an operating state of the storage device. The method includes receiving, by the controller and from a host device, a non-interrupt command frame that requests transfer of data blocks between the storage device and the host device. The method further includes, in response to receiving the non-interrupt command frame, generating, by the controller, a response frame associated with the non-interrupt command frame, wherein the response frame includes the operating statistics. The method includes transmitting, by the controller and to the host device, the response frame.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 7, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mark David Erickson, Darin Edward Gerhart, Nicholas Edward Ortmeier
  • Patent number: 9990291
    Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 5, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hien Minh Le, Thuong Quang Truong, Kun Xu, Jaya Prakash Subramaniam Ganasan, Cesar Aaron Ramirez
  • Patent number: 9986022
    Abstract: In one embodiments, one or more first computing devices receive updated values for user data associated with a plurality of users; and for each of the user data for which an updated value has been received, determine one or more second systems that each have subscribed to be notified when the value of the user datum is updated and each have a pre-established relationship with the user associated with the user datum; and push notifications to the second systems indicating that the value of the user datum has been updated without providing the updated value for the user datum to the second systems.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 29, 2018
    Assignee: Facebook, Inc.
    Inventors: Wei Zhu, Ray C. He, Luke Jonathan Shepard
  • Patent number: 9933962
    Abstract: Methods, computer media encoding instructions, and systems that receive write requests directed to non-sequential logical block addresses and write the write requests to sequential disk block addresses in a storage system include an overprovision of a storage system to include an increment of additional storage space such that it is more likely a large enough sequential block of storage will be available to accommodate incoming write requests.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: April 3, 2018
    Assignee: Open Invention Network, LLC
    Inventors: Alan Rowe, Chandrika Srinivasan, Sameer Narkhede, Wing Yee Au, Ismail Dalgic
  • Patent number: 9921964
    Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.
    Type: Grant
    Filed: January 7, 2017
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Chung-Lung Kevin Shum, Kathryn Marie Jackson, Charles Franklin Webb
  • Patent number: 9921764
    Abstract: Provided are a computer program product, system, and method for using inactive copy relationships to resynchronize data between storages. A first and second groups of active copy relationships are established to serially copy data among the storages in the first and second groups, respectively. At least one of the storages in both the first group and the second group comprise overlapping storages that are members of both the first and second groups and at least one of the storages in both the first and second groups comprise non-overlapping storages that are a member of only one of the first and second groups. At least one inactive copy relationship is established having as a source storage one of the non-overlapping storages in the first group and as a target storage one of the non-overlapping storages in the second group.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Brian D. Hatfield
  • Patent number: 9921770
    Abstract: Systems and procedures are provided to enable fixed block architecture (FBA) device support over fiber connections using transport mode protocol. The FBA devices may have a size greater than 2 terabytes. The system may be used with existing fixed block command sets according to the transport mode protocol. The existing fixed block command sets may be extended to permit addressing of greater than 2 terabytes. The transport mode protocol may be based on a high performance protocol implementation that facilitates processing of I/O requests.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 20, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Martin J. Feeney, Douglas E. LeCrone
  • Patent number: 9921965
    Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.
    Type: Grant
    Filed: January 7, 2017
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Chung-Lung Kevin Shum, Kathryn Marie Jackson, Charles Franklin Webb
  • Patent number: 9916899
    Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey McVay, Daniel Dillon, Laine Walker-Avina
  • Patent number: 9910789
    Abstract: A processor issues a command to a memory through an electrical memory link and performs a process according to the command through the electrical memory link. The processor issues a routing command to an optical circuit switch (OCS) through an OCS control line. In response to the routing command, the OCS establishes a routing of an optical memory link from the processor to the BDM. In response to the establishment of the optical memory link from the processor to the BDM, the processor (or a BDM (internal/dedicated) controller) switches from performing the process through the electrical memory link to performing a process through the optical memory link (continuously without an interruption between the successive processes). Corresponding systems are also disclosed herein.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Yasunao Katayama, Seiji Muneto, Atsuya Okazaki
  • Patent number: 9904472
    Abstract: A memory system and method for delta writes are provided. In one embodiment, a memory system receives a request to store data in the memory and determines whether the data requested to be stored in the memory is a modified version of data already stored in the memory. If it is, the memory system compares the data requested to be stored in the memory with the data already stored in the memory to identify differences between the data to be stored and the data already stored. The memory system then stores the identified differences in the memory, along with a table that maps the stored identified differences to corresponding locations in the data already stored in the memory. Other embodiments are provided.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: February 27, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel E. Tuers, Abhijeet Manohar, Judah Gamliel Hahn
  • Patent number: 9898222
    Abstract: Described are various SoC fabric extensions for configurable memory mapping. A memory request datapath may transmit a memory request. A first circuitry may identify any memory request having an address between a base-address and limit-address. A second circuitry may transmit to a memory interface any memory request that is identified by the first circuitry, and to apply a default memory access protocol to any memory request that is unidentified by the first circuitry. A third circuitry may modify an address of a memory request when both a multiple-memory-interface indicator and an address-flattening indicator are asserted.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: February 20, 2018
    Assignee: Intel IP Corporation
    Inventor: Jose S. Niell
  • Patent number: 9898202
    Abstract: A system and method for using a Solid State Drive (SSD) (505) are described. Reception circuitry (510) may receive write requests (1610, 1615, 1620, 1625) and invalidate requests (1630, 1635, 1640) from a first stream (305, 320, 335, 350). The write requests (1610, 1615, 1620, 1625) may request that data be written to storage (520) on the SSD (505); invalidate requests (1630, 1635, 1640) may invalidate data written to the storage (520). A statistics calculation logic (1705) may calculate statistics (1410, 1415, 1510) for the stream based on the write requests (1610, 1615, 1620, 1625) and the invalidate requests (1630, 1635, 1640). A performance logic (1710) may use the calculated statistics (1410, 1415, 1510) to improve the performance of the SSD (505).
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jason Martineau, William David Schwaderer, Changho Choi
  • Patent number: 9892038
    Abstract: A data caching method is disclosed. The method comprises changing, according to an instruction, a cache value, corresponding to a key, in a cache on a volatile memory, recording the instruction following a first effective content of a log file in a non-volatile memory to obtain a second effective content, the second effective content including the first effective content and the recorded instruction, and storing the key and the changed cache value corresponding to the key into the non-volatile memory.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: February 13, 2018
    Assignee: GUANGZHOU UCWEB COMPUTER TECHNOLOGY CO., LTD.
    Inventors: Jie Liang, Jian Wu
  • Patent number: 9892040
    Abstract: A semiconductor memory device includes: a memory cell array including memory strings, one of the memory strings including memory cells; word lines commonly connected to the memory strings; and a controller configured to execute a write operation and a read operation on a page, the page being stored in memory cells connected to one of the word lines. The controller is configured to measure a cell current flowing in the memory string, and adjust a write voltage applied to a word line, based on a result of the cell current.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe
  • Patent number: 9886304
    Abstract: Disclosed herein are various systems and methods for sharing a storage device with multiple virtual machines are disclosed. One such method involves creating a pseudo-identity for a storage device and assigning a portion of an address space of the storage device to a virtual machine using the pseudo-identity. The storage device is coupled to a computing device and the pseudo-identity is created by a hypervisor associated with the computing device. The pseudo-identity facilitates access to the storage device by the virtual machine associated with the hypervisor and also facilitates presentation of one or more physical characteristics of the storage device to the virtual machine. The method also assigns a portion of an address space of the storage device to the virtual machine using the pseudo-identity.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: February 6, 2018
    Assignee: Veritas Technologies LLC
    Inventor: Hari Krishna Vemuri
  • Patent number: 9880938
    Abstract: In accordance with an embodiment, described herein is a system and method for compacting a pseudo linear byte array, for use with supporting access to a database. A database driver (e.g., a Java Database Connectivity (JDBC) driver) provides access by software application clients to a database. When a result set (e.g., ResultSet) is returned for storage in a dynamic byte array (DBA), in response to a database query (e.g., a SELECT), the database driver determines if the DBA is underfilled and, if so, calculates the data size of the DBA, creates a static byte array (SBA) in a cache at the client, compacts the returned data into the SBA, and stores the data size as part of the metadata associated with the cache. In accordance with an embodiment, the DBA and the SBA can use a same interface for access by client applications.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: January 30, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Ashok Shivarudraiah, Douglas Surber, Jean De Lavarene
  • Patent number: 9877065
    Abstract: A device is provided for use with a content provider that is operable to provide content, which includes a plurality of content components. The device includes a communication portion, a memory portion, a parsing portion, a counting portion and a processing portion. The communication portion can receive the content from the content provider. The parsing portion can parse the content into the plurality of content components and can store the parsed plurality of content components within the memory portion. The counting portion can provide a counter for each of the parsed plurality of content components within the memory portion, respectively. The processing portion can retrieve and process one of the parsed plurality of content components within the memory portion. The counting portion can further increment the counter associated with the retrieved one of the parsed plurality of content components within the memory portion.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 23, 2018
    Assignee: Google Technology Holdings LLC
    Inventor: Krishna Prasad Panje
  • Patent number: 9864682
    Abstract: According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doohyun Kim, BoGeun Kim, Kitae Park, Jinman Han
  • Patent number: 9857983
    Abstract: A flash translation layer table rebuilding method for a solid state drive is provided. The solid state drive includes a non-volatile memory and a buffering circuit. Firstly, a flash translation layer table is loaded from the non-volatile memory to the buffering circuit. In case that an abnormal shutdown event occurs, plural blocks of the non-volatile memory to be read are determined according to a specified block programming serial number of the flash translation layer table. Then, a read sequence of reading the plural blocks is determined according to a block programming serial number or an auxiliary serial number corresponding to the block. The contents of the blocks are read according to the read sequence. A mapping relationship between plural physical allocation addresses and plural logical block addresses of the flash translation layer table is updated.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 2, 2018
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Liang-You Lin, Yu-Chuang Peng, Ya-Ping Pan, Ho-An Lin