Abstract: A storage system is configured to accept subsequent versions of write data on a given track to multiple respective slots of shared global memory. A track index table presents metadata at the track level, and can hold up to N slots of data. All slots of shared global memory holding data owed to the source volume and to snapshots of the source volume are bound to the track in the track index table. Each time a write occurs on a track, the track index table is used to determine when a write pending slot for the track is owed to a snapshot copy of the storage volume. When a write pending slot contains data that is owed to a snapshot copy of the source volume, a new slot is allocated to the write IO and bound to the track in the track index table.

Abstract: A programming order of memory dies of a metablock is typically fixed. However, in some storage architectures, this may cause performance bottlenecks. As such, the programming order of the memory dies may be altered to reduce or eliminate performance bottlenecks.

Abstract: Disclosed is an operation method of a memory device which performs a self-refresh operation. The method includes receiving a deep-sleep mode enter command from a memory controller, changing a magnitude of an internal voltage of the memory device from a first voltage to a second voltage smaller than the first voltage, in response to the deep-sleep mode enter command, and entering a self-refresh mode under control of the memory controller, and the internal voltage is maintained at the second voltage during the self-refresh mode.

Abstract: Various embodiments include a computer memory system that dynamically adjusts a memory device performance feature, such as dynamic assist control, dynamic turbo mode, and/or the like, to improve the performance of memory devices in the memory system. The memory system enables or disables the memory device performance feature based on the operating voltage relative to a threshold voltage. If the operating voltage crosses the threshold voltage in one direction, then the memory device system enables the memory device performance feature. If the operating voltage crosses the threshold voltage in another direction, then the memory system disables the memory device performance feature. Various techniques enable the memory device performance feature to be employed even with complex integrated circuits that may include tens of thousands of devices that employ the memory device performance feature.

Abstract: A method for remapping a virtual address to a physical address is provided. The method is used in an address remapping unit and includes: receiving, by a remapping processing unit of the address remapping unit, a remapping request, decoding the remapping request and determining whether the remapping request has a direct memory access (DMA) remapping request; and executing, by the remapping processing unit, a remapping procedure: translating a virtual address corresponding to the remapping request to a physical address, when the remapping request has the DMA remapping request.

Abstract: A data storage device may include a storage and a controller. The storage a storage including a first region of a first physical address range and a second region of a second physical address range. The controller may generate map data including a plurality of map segments, a first segment entry and a second segment entry, and store, in the second region, the map data except for a first map segment. Each of the map segments includes a set of physical addresses corresponding to a plurality of sequential logical addresses. The first segment entry includes a first segment physical address associated with the first map segment and belonging to the first physical address range, and the second segment entry includes a second segment physical address associated with a second map segment and belonging to the second physical address range.

Abstract: A memory system includes: a first nonvolatile memory; a second volatile memory; a controller; a power control circuit configured to perform control such that a first voltage is applied to the first memory, the second memory, and the controller based on first power supplied from an external power supply; and a power storage device configured to supply second power to the power control circuit while the first power from the external power supply is interrupted. While the first power supplied from outside is interrupted, the power control circuit applies a second voltage based on the second power supplied from the power storage device to the first memory, the second memory, and the controller. The power control circuit stops the application of the second voltage to the second memory after the data is read from the second memory and before the data is written into the first memory.

Abstract: A method for operating a memory system includes: collecting, by a memory controller, information on rows that are determined as row-hammer-attacked in a memory by the memory controller; collecting, by the memory, information on rows that are determined as row-hammer-attacked by the memory; confirming, by the memory, that the row collected by the memory controller is the same as the row collected by the memory; and resetting, by the memory, information on the row collected by the memory which is the same as the row collected by the memory controller in response to the confirmation.

Abstract: Exemplary methods, apparatuses, and systems including an adaptive configuration manager for controlling configurations of memory devices. The adaptive configuration manager receives a plurality of payloads from a host. The adaptive configuration manager identifies a profile of the host from a plurality of pre-determined host profiles. The adaptive configuration manager identifies a distribution of the plurality of memory access requests, the distribution including a set of sequential payloads and a set of random payloads. The adaptive configuration manager generates a memory access command using the profile of the host including a distribution of random and sequential access. The adaptive configuration manager executes the memory access command using the profile and a payload of the plurality of payloads.

Abstract: In one embodiment, a bounding box prefetch unit in a microprocessor, the bounding box prefetch unit comprising: storage comprising a plurality of active prefetcher state entries for storing state information for a corresponding plurality of access streams associated with load requests, and a corresponding plurality of prediction logic; and a prefetcher state cache comprising plural prefetcher state entries that do not match any of the active prefetcher state entries.

Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

Abstract: An apparatus includes an interface circuit and a monitor circuit communicatively coupled to the interface circuit. The monitor circuit is configured to identify a command issued to a memory communicatively coupled to the monitor circuit through the interface circuit, determine whether the command is authorized, and, based on a determination that the command is not authorized, cancel the command.

Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

Abstract: It is one object of the present disclosure to provide measures for securing scalability of the queue depth of cache schedulers by utilizing a plurality of cache schedulers. To this end, a cache memory device in accordance with one embodiment of the present disclosure comprises: a request reception unit configured to receive input transactions; a traffic monitoring module configured to monitor traffic of the input transactions; N cache schedulers, wherein N is an integer greater than or equal to 2; a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers.

Abstract: Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.

Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a data security indicator, and a controller. The controller is configured to selectively control access of the host computer system to the user data based on security configuration data of the data storage device. The controller is further configured to respond to the occurrence of one or more operations, the operations being any of: (i) a data access operation requested or performed, by the host computer system, on the data storage device to access the storage medium via the data port; and (ii) a security control operation requested or performed, by an external device, on the data storage device to store, retrieve or update the security configuration data of the data storage device.

Abstract: In a management node that manages a distributed file and object storage that accessibly manages a file used by an application, the distributed file and object storage is accessible to a file managed by a storage of another site, and a management node includes a processor, and the processor is configured to specify an access circumstance relating to a file by an application, and control caching by the distributed file and object storage of the own site with respect to the file managed by the storage of the other site used by the application, before the application is executed, based on the access circumstance.

Abstract: An approach allows concurrent execution of near-memory processing commands, referred to herein as “PIM commands,” and host memory commands. A memory controller determines and issues a plurality of register-only PIM commands that do not reference memory with host memory commands to allow concurrent execution of the register-only PIM commands and the host memory commands. The approach allows concurrent execution of register-only PIM commands and host memory commands without interference, even when the register-only PIM commands and the host memory commands are interleaved, and even for the same memory module, which improves resource utilization and performance. Further improvement of resource utilization and performance is achieved by extending a register-only phase by reordering register-only PIM commands before non-register-only PIM commands, subject to dependency constraints, and using shadow row buffers to provide local working copies of data from memory to near-memory compute elements.

Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

Abstract: Purging resources from a cache in a distributed networked system is described. A first data center of the distributed networked system receives a purge request to purge a resource from cache. If the purge request does not include a cache key, the first data center determines whether the purge request is valid, and if valid, purges the resource from cache of the first data center, generates a cache key for the resource, and causes the purge request that includes the generated cache key to be sent to other data centers of the distributed networked system for purging the resource from cache. If the purge request includes a cache key, the first data center skips determining whether the purge request is valid and purges the resource from cache based on the cache key.