Patents Examined by Pierre-Michel Bataille
  • Patent number: 11921638
    Abstract: According to some embodiments of the present invention, there is provided a hybrid cache memory for a processing device having a host processor, the hybrid cache memory comprising: a high bandwidth memory (HBM) configured to store host data; a non-volatile memory (NVM) physically integrated with the HBM in a same package and configured to store a copy of the host data at the HBM; and a cache controller configured to be in bi-directional communication with the host processor, and to manage data transfer between the HBM and NVM and, in response to a command received from the host processor, to manage data transfer between the hybrid cache memory and the host processor.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Krishna T. Malladi, Hongzhong Zheng
  • Patent number: 11914865
    Abstract: A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yamin Friedman, Idan Burstein, Hillel Chapman, Gal Yefet
  • Patent number: 11914517
    Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 27, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sergey Blagodurov, Marko Scrbak, Brandon K. Potter
  • Patent number: 11893277
    Abstract: A data storage device is disclosed comprising a head actuated over a disk, a first semiconductor memory (SM) having a first endurance, and a second SM having a second endurance lower than the first endurance. A write command is received from a host including write data. When a size of the write command is less than a threshold, the write data is stored in a first SM write cache in the first SM, and when the size of the write command is greater than the threshold, the write data is stored in a second SM write cache in the second SM.
    Type: Grant
    Filed: February 20, 2021
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: David R. Hall
  • Patent number: 11893249
    Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 6, 2024
    Assignee: Ceremorphic, Inc.
    Inventors: Subba Reddy Kallam, Partha Sarathy Murali, Venkata Siva Prasad Pulagam, Anusha Biyyani, Venkatesh Vinjamuri, Shahabuddin Mohammed, Rahul Kumar Gurram, Akhil Soni
  • Patent number: 11886345
    Abstract: Configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system is disclosed. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. In response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • Patent number: 11880678
    Abstract: A chip includes a power pin, a ground pin, a plurality of input/output (I/O) pins, a readable/writable memory, a switching circuit, and a control circuit. The I/O pins include a plurality of mapping pins and a control pin. The readable/writable memory includes a clock port, a plurality of I/O ports, and an enable port. The control circuit selectively activates or does not activate the switching circuit according to the control pin. When the switching circuit is activated, the switching circuit electrically couples the clock port, the I/O ports, and the enable port to the mapping pins respectively.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: January 23, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Neng-Hsien Lin, Wan-Pei Geng, Yao Feng, Chen Shen
  • Patent number: 11874774
    Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 16, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ravindra N. Bhargava, Ganesh Balakrishnan, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam
  • Patent number: 11874776
    Abstract: Methods and apparatus relating to cryptographic protection of memory attached over interconnects are described. In an embodiment, memory stores data and a processor having execution circuitry executes an instruction to program an inline memory expansion logic and a host memory encryption logic with one or more cryptographic keys. The inline memory expansion logic encrypts the data to be written to the memory and decrypts encrypted data to be read from the memory. The memory is coupled to the processor via an interconnect endpoint of a system fabric. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 16, 2024
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Prashant Dewan
  • Patent number: 11868273
    Abstract: Embodiments are directed to memory protection with hidden inline metadata to indicate data type and capabilities. An embodiment of a processor includes a processor core and cache memory. The processor core is to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata hidden at a linear address level, hidden from software, the hidden inline metadata to indicate data type or capabilities for the associated data stored on the same cacheline.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventor: David M. Durham
  • Patent number: 11868247
    Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: January 9, 2024
    Assignee: Radian Memory Systems, Inc.
    Inventors: Andrey V. Kuzmin, James G. Wayda
  • Patent number: 11861194
    Abstract: According to one embodiment, a storage device is configured to store unencrypted user data. The user data is erased according to at least one data erasure mechanism. The storage device comprises a receiver configured to receive an inquiry from a host device, and a transmitter configured to transfer response information indicating the at least one data erasure mechanism to the host device.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Hiroshi Isozaki, Teruji Yamakawa
  • Patent number: 11853211
    Abstract: A data placement program causes a computer to execute a process of data placement in a main memory and a cache. When performing an operation using a first data groups and second data groups to generate pieces of operation result data representing operation results of the operation, based on a size of one piece of the operation result data and a size of an operation result area storing some of the plurality of pieces of operation result data in the cache memory, determining a number of the first data groups and a number of the second data groups, both corresponding to the some pieces of operation result data, and placing the plurality of first data groups and the plurality of second data groups in the main memory based on the determined number of the first data groups and the determined number of the second data groups.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: December 26, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Yukihiro Komura
  • Patent number: 11853593
    Abstract: Methods and systems for managing communications is disclosed. A host device and a management controller may communicate via memory mapped communications using shared memory. To improve the security of the memory mapped communications, access requests for shared memory may be monitored. Access controls for the shared memory may be put in place to reduce the likelihood of data being made unavailable before it is processed. The access controls may be lifted when the data stored in shared memory has been read by to complete the memory mapped communications.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: December 26, 2023
    Assignee: Dell Products L.P.
    Inventors: Bassem Elazzami, Adolfo Sandor Montero, Ibrahim Sayyed
  • Patent number: 11847067
    Abstract: Methods and apparatus relating to cryptographic protection of memory attached over interconnects are described. In an embodiment, memory stores data and a processor having execution circuitry executes an instruction to program an inline memory expansion logic and a host memory encryption logic with one or more cryptographic keys. The inline memory expansion logic encrypts the data to be written to the memory and decrypts encrypted data to be read from the memory. The memory is coupled to the processor via an interconnect endpoint of a system fabric. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Prashant Dewan
  • Patent number: 11847054
    Abstract: A processing system server and methods for performing asynchronous data store operations. The server includes a processor which maintains a cache of objects in memory of the server. The processor executes an asynchronous computation to determine the value of an object. In response to receiving a request for the object occurring before the asynchronous computation has determined the value of the object, a value of the object is returned from the cache. In response to receiving a request for the object occurring after the asynchronous computation has determined the value of the object, a value of the object determined by the asynchronous computation is returned. The asynchronous computation may comprise at least one future, such as a ListenableFuture, or a process or thread. The asynchronous computation may determine the value of the object by querying at least one additional server.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: December 19, 2023
    Assignee: International Business Machines Corporation
    Inventor: Arun Iyengar
  • Patent number: 11836088
    Abstract: Guided cache replacement is described. In accordance with the described techniques, a request to access a cache is received, and a cache replacement policy which controls loading data into the cache is accessed. The cache replacement policy includes a tree structure having nodes corresponding to cachelines of the cache and a traversal algorithm controlling traversal of the tree structure to select one of the cachelines. Traversal of the tree structure is guided using the traversal algorithm to select a cacheline to allocate to the request. The guided traversal modifies at least one decision of the traversal algorithm to avoid selection of a non-replaceable cacheline.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: December 5, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jeffrey Christopher Allan
  • Patent number: 11822815
    Abstract: Ring buffer storage circuitry is disclosed which stores a ring buffer comprising multiple slots to hold a queued se-quence of data items. Data processing circuitry executes a plurality of processes to add one or more data items to be processed to the queued sequence and to remove one or more data items for process-ing from the queued sequence. Each process is arranged to perform an acquire process to acquire at least one slot in the ring buffer and to subsequently perform a release process to release the at least one slot. Ring buffer metadata storage circuitry stores metadata for the ring buffer comprising a first reference indicator and a second reference indicator. Corresponding methods and instructions are also disclosed.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: November 21, 2023
    Assignee: Arm Limited
    Inventor: Eric Ola Harald Liljedahl
  • Patent number: 11809318
    Abstract: Described herein are systems, methods, and non-transitory computer readable media for memory address encoding of multi-dimensional data in a manner that optimizes the storage and access of such data in linear data storage. The multi-dimensional data may be spatial-temporal data that includes two or more spatial dimensions and a time dimension. An improved memory architecture is provided that includes an address encoder that takes a multi-dimensional coordinate as input and produces a linear physical memory address. The address encoder encodes the multi-dimensional data such that two multi-dimensional coordinates close to one another in multi-dimensional space are likely to be stored in close proximity to one another in linear data storage. In this manner, the number of main memory accesses, and thus, overall memory access latency is reduced, particularly in connection with real-world applications in which the respective probabilities of moving along any given dimension are very close.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: November 7, 2023
    Assignee: Pony AI Inc.
    Inventors: Yubo Zhang, Pingfan Meng
  • Patent number: 11809221
    Abstract: An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: November 7, 2023
    Assignee: Shanghai Biren Technology Co., Ltd
    Inventors: Zhou Hong, Qin Zheng, ChengPing Luo, GuoFang Jiao, Song Zhao, XiangLiang Yu