Abstract: Apparatuses for address expansion and methods of address expansion are disclosed. Memory region definitions are stored, each comprising attribute data relevant to a respective memory region. In response to reception of a first address a region identifier indicative of a memory region to which the first address belongs is provided. Cache storage stores data in association with an address tag and in response to a cache miss a data retrieval request is generated. Address expansion circuitry is responsive to the data retrieval request to initiate a lookup for attribute data relevant to the memory region to which the first address belongs. The address expansion circuitry expands the first address in dependence on a base address forming part of the attribute data to generate an expanded second address, wherein the expanded second address is part of greater address space than the first address.

Abstract: A data processing system includes a plurality of snoopers, a processing unit including master, and a system fabric communicatively coupling the master and the plurality of snoopers. The master sets a retry operating mode for an interconnect operation in one of alternative first and second operating modes. The first operating mode is associated with a first type of snooper, and the second operating mode is associated with a different second type of snooper. The master issues a memory access request of the interconnect operation on the system fabric of the data processing system. Based on receipt of a combined response representing a systemwide coherence response to the request, the master delays an interval having a duration dependent on the retry operating mode and thereafter reissues the memory access request on the system fabric.

Abstract: Systems, apparatuses, and methods for implementing a multi-tiered approach to cache compression are disclosed. A cache includes a cache controller, light compressor, and heavy compressor. The decision on which compressor to use for compressing cache lines is made based on certain resource availability such as cache capacity or memory bandwidth. This allows the cache to opportunistically use complex algorithms for compression while limiting the adverse effects of high decompression latency on system performance. To address the above issue, the proposed design takes advantage of the heavy compressors for effectively reducing memory bandwidth in high bandwidth memory (HBM) interfaces as long as they do not sacrifice system performance. Accordingly, the cache combines light and heavy compressors with a decision-making unit to achieve reduced off-chip memory traffic without sacrificing system performance.

Abstract: In at least one embodiment, a processing unit includes a processor core and a vertical cache hierarchy including at least a store-through upper-level cache and a store-in lower-level cache. The upper-level cache includes a data array and an effective address (EA) directory. The processor core includes an execution unit, an address translation unit, and a prefetch unit configured to initiate allocation of a directory entry in the EA directory for a store target EA without prefetching a cache line of data into the corresponding data entry in the data array. The processor core caches in the directory entry an EA-to-RA address translation information for the store target EA, such that a subsequent demand store access that hits in the directory entry can avoid a performance penalty associated with address translation by the translation unit.

Abstract: An information handling system for compressing data includes a data storage device and a processor. The data storage device stores a dictionary and an uncompressed data block. The processor prepends the dictionary to the uncompressed data block, determines, from the uncompressed data block, a literal data string and a match data string where the match data string is a matching entry of the dictionary, and compresses the uncompressed data block into a compressed data block that includes the literal data string and an offset pointer that points to the matching entry.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: Disclosed herein are techniques for management of a non-volatile memory device. In one example, an integrated circuit comprises a cache device and a management controller. The cache device is configured to store a first mapping between logical addresses and physical addresses of a first memory, the first mapping being a subset of mapping between logical addresses and physical addresses of the first memory stored in a second memory, and an access count associated with each of the physical addresses of the first mapping. The management controller is configured to: maintain access statistics of the first memory based on the access counts stored in the cache device; and determine the mapping between logical addresses and physical addresses stored in the second memory based on the access statistics and predicted likelihoods of at least some of the logical addresses receiving an access operation.

Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

Abstract: In a controller that operates a control program which executes sequence control or the like together with a data processing program which executes a complex arithmetic operation or the like, I/O resource information is shared with a shared memory, and an access right to the I/O resource information by the data processing program is controlled using read-in prohibited information and write-in permitted information.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: Described embodiments include memory systems that may shadow certain data stored in a first memory device (e.g. NAND flash device) onto a second memory device (e.g. DRAM device). Memory systems may train and/or re-organize stored data to facilitate the selection of data to be shadowed. Initial responses to memory commands may be serviced from the first memory device, which may have a lower latency than the second memory device. The remaining data may be serviced from the second memory device. A controller may begin to access the remaining data while the initial response is being provided from the first memory device, which may reduce the apparent latency associated with the second memory device.

Abstract: A memory module including at least one memory and a memory control circuit to control the at least one memory and to generate an internal operation request including an information regarding internal operation time when the memory module need the internal operation time. The memory control circuit is to transfer the internal operation request to an external device, to receive a first command from the external device in response to the internal operation request and including an information of whether the internal operation time is approved, and to perform the internal operation during the internal operation time based on the first command.

Abstract: Aspects of a storage device including a controller are provided which identifies a bad, open block that causes subsequent erase operations to fail in closed blocks due to charge leakage following a previous program operation in the open block. Each time the controller programs an open block, the controller attempts to erase a plurality of closed blocks following each programming of the open block. When the closed blocks fail to erase, the controller determines whether a number of consecutive erase failures after programming the open block meets a threshold, after which the controller re-attempts to erase the closed blocks. After a successful re-attempt, the controller stores a list of open blocks in memory. In response to repeating these steps a number or plurality of times, the controller stores multiple lists of open blocks in memory, and identifies the single common open block between the multiple lists as a bad block.

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

Abstract: Aspects of the disclosure provide for implementing host address space identifiers for non-uniform memory access (NUMA) locality in virtual machines. A method of the disclosure includes determining, by a virtual machine (VM) executed by a processing device and managed by a hypervisor, that a memory page of the guest is to be moved from a first virtual non-uniform memory access (NUMA) node of the VM to a second virtual NUMA node of the VM. The method further includes updating, by the VM in a guest page table, upper bits of a guest physical address (GPA) of the memory page to include a host address space identifier (HASID) of the second virtual NUMA node, and causing an execution control to be transferred from the VM to the hypervisor due to a page fault resulting from attempting to access the updated GPA.

Abstract: A system includes a first counter configured to increment or decrement in response to a triggering event. The first counter is sized to overflow. The system also includes a second counter configured to increment or decrement in response to a triggering event. The first counter and the second counter are merged to form a third counter in response to detecting an overflow triggering event for the first counter. A merge bit indicative of whether the first counter and the second counter are merged changes value in response to merging the first counter and the second counter.

Abstract: Methods, systems, and computer-readable media for a bulk ingestion interface for a distributed data storage system are described. A bulk ingestion interface may allow bulk data to be ingested into a distributed data storage system using compute resources separate from respective compute resources of the distributed data storage system used to perform access requests to datasets stored on one or more resource hosts of the distributed data storage system.

Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

Abstract: A memory system includes: a memory device including a plurality of memory blocks each having a plurality of pages suitable for storing data; and a controller suitable for: receiving a plurality of commands from a host; controlling the memory device to perform a plurality of command operations in response to the plurality of commands; identifying parameters for the memory blocks affected by the command operations performed to the memory blocks; selecting first memory blocks among the memory blocks according to the parameters; and controlling the memory device to swap data stored in the first memory blocks to second memory blocks among the memory blocks.

Abstract: A storage control device operable to be one of a plurality of storage control devices included in a storage device, the storage control device includes: a memory; and a processor coupled to the memory, the processor being configured to processing, the processing including: executing a determination processing that includes determining whether activation of the storage control device is caused by activation of the entire storage device or activation of the storage control device alone; and executing a region setting processing that includes setting a control information storage region that stores control information used to enable a function of the storage device according to a determination result by the determination processing.