Patents Examined by Po C. Huang
  • Patent number: 6038379
    Abstract: A computer network having a number of workstations running disparate operating systems and a file server having a tape drive for backup and restore of data on the network. The file server runs a generic remote file system (GRFS) and workstations run GRFS agent programs which allow the GRFS file system to access data within a workstation having a given GRFS agent program. The GRFS file system interfaces with each GRFS agent program via a command/response paradigm, with the messages being structured to support the disparate operating systems for backup and restore, to allow data to be interchanged between the disparate operating systems, and to allow independent multiple users of the network to request simultaneously backup or restore.
    Type: Grant
    Filed: October 11, 1995
    Date of Patent: March 14, 2000
    Assignee: Seagate Technology, Inc.
    Inventors: Douglas J. Fletcher, Steven Robert DeVos
  • Patent number: 5983025
    Abstract: Buffers are provided in a computer system to allow posting data to the buffers, followed by concurrent operation by different portions of the computer system. A CPU buffer is provided to buffer CPU accesses, a CPU-to-PCI buffer is provided to buffer CPU accesses to the PCI local bus, and a memory buffer is provided to buffer CPU accesses to main memory. This configuration allows the CPU-to-PCI buffer to write data concurrently with the memory buffer accessing data from main memory.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 9, 1999
    Assignee: International Business Machines Corporation
    Inventors: John Edward Derrick, William R. Greer, Christopher Michael Herring
  • Patent number: 5870615
    Abstract: A PCMCIA card having cellular phone battery charging circuitry, and an adapter cable having a PCMCIA card connector equipped with a battery characteristic encoder, are provided to charge a cellular phone battery, using power supplied by a mobile PC, in accordance to battery characteristic information provided by the battery characteristic encoder. Starting and stopping of charging operation is preferably controlled by mobile PC. Furthermore, starting and stopping of charging operation is preferably automated with charging software application executing on mobile PC.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: February 9, 1999
    Assignee: Intel Corporation
    Inventors: David Bar-On, Dan Gavish
  • Patent number: 5838991
    Abstract: A method and apparatus for performing preemptable calibration and housekeeping functions during idle time between commands thereby maximizing data throughput. The idle time activities are scheduled on an infrequent time scale. A single seek is used to get to a measurement location. Once the read/write head is positioned at the measurement location, it stays there for a fairly long time in order to make many measurements. If a new host command arrives, the test is aborted and the host command is serviced. The new command is begun without performing any clean-up activity and may or may not record the point at which the idle time activity was abandoned and idle time activity is reinitiated after the new command is completed. Results from the idle time activity is committed to the disk or RAM only after completion of an idle time activity, and thereafter another idle time activity is begun.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: November 17, 1998
    Assignee: International Business Machines Corporation
    Inventor: James R. Shipman
  • Patent number: 5828898
    Abstract: A microcomputer includes an input terminal, coupled to the control terminal of a transmission gate, that receives a real-time request signal asserted by a peripheral. The transmission gate transfers data from a register to the peripheral in synchronism with the assertion of the real-time request signal so that data is provided to the peripheral in real time.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: October 27, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuhiro Ami, Takeshi Fujii
  • Patent number: 5819112
    Abstract: An improved operating system for a personal computer including a method for controlling a parallel I/O port for peer-to-peer communication is disclosed. The improved operating system includes a port driver which supports communication with multiple peripheral devices through a single parallel port. The peripheral devices are connect to the parallel port via a multiplexer and may include non-interrupt devices, master/slave devices, and peer-to-peer devices. The parallel port driver includes a port arbitrator and a plurality of class device drivers to control access to the parallel port. Each class device driver communicates with a particular class of devices connected to the port. The port arbitrator controls access to port by the various class device drivers. The parallel port includes configurable control registers that include interrupt control bits for enabling and disabling interrupts communicated by peripheral devices.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: October 6, 1998
    Assignee: Microsoft Corporation
    Inventor: Norbert Paul Kusters
  • Patent number: 5812875
    Abstract: The present invention is directed to improving the time with which information transfer signals can be generated in response to an initiating signal. Exemplary embodiments are described in the context of a small computer system interface, wherein enhanced operation is achieved by producing a response signal, such as an acknowledge signal, in close proximity to receipt of an initiating signal, such as a request signal. Further, exemplary embodiments achieve such improved operation without the use of complex circuitry; rather, relatively simple latching circuitry is provided in accordance with the present invention to substantially increase overall operating efficiency.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: September 22, 1998
    Assignee: Apple Computer, Inc.
    Inventor: Michael K. Eneboe
  • Patent number: 5809330
    Abstract: Among devices on the system board, all devices other than those devices essential to the operation of the system such as system timer 19 and real-time clock 20, i.e., I/O devices 24 and 25, are constructed such that their environment may be configured and changed. If the hardware resources allocated to I/O devices 24 and 25, such as I/O address areas, interrupt levels, etc., overlap with the hardware resources requested by option cards 32 or 33, the hardware resources allocated to I/O devices 24 and 25 are automatically changed. As a result, the internal I/O devices and option boards can always be made to operate normally, regardless of the values set for the I/O address areas, etc., for option cards 32 and 33.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: September 15, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryoji Ninomiya
  • Patent number: 5805923
    Abstract: A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interface circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: September 8, 1998
    Assignee: Sony Corporation
    Inventor: Michael John Shay
  • Patent number: 5805931
    Abstract: A programmable bandwidth I/O port using a DRAM connected to a plurality of serial access memories. Data is synchronously transferred between the DRAM and the serial access memories and is asynchronously transferred between the serial access memories and a plurality of single or multiple bit I/O ports. The bus widths of the I/O ports may be easily programmed to provide a wide variety of I/O port configurations.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: September 8, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Christopher K. Morzano, Charles L. Ingalls
  • Patent number: 5799207
    Abstract: A computer system is disclosed which has a master, such as a processor, a memory, and I/O device, a first transfer path, which includes a bus, and a second transfer path, which includes a transfer interconnection. Transfers between the memory and the I/O device are effected via the first path while transfers between the processor and the I/O device are transferred via the second path. The disparate treatment between these two types of transfers reduces the likelihood that the transfer via the second path is delayed and thereby reduces the likelihood that the master is totally blocked from operation.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: August 25, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Chieh Wang, Wei-Wen Chang, Zen-Dar Hsu
  • Patent number: 5797036
    Abstract: An I/O control system for a general-purpose computer having multiple bus branches separated by routing circuitry prepares a digital map of I/O device locations on the bus branches, and copies versions of the maps to registers in the routing circuitry on startup and reset. The routing maps provide immediate routing information for I/O requests issued by one or more CPUs in a system, allowing the routing circuitry between bus branches to immediately route requests to the proper device with a minimum of wait states. In one aspect I/O devices are polled for location at startup and reset, and in another aspect, a universal map protocol is a part of the BIOS or storage accessible by the BIOS, making a system self-configuring and providing the necessary information for the mapping for the routing circuitry.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: August 18, 1998
    Assignee: Elonex I.P. Holdings, Ltd.
    Inventor: Dan Kikinis
  • Patent number: 5793982
    Abstract: An installation plan object including application objects representing applications to be installed during an installation process and workstation objects representing the workstation on which the applications are to be installed is validated prior to executing the installation plan. According to the invention, multiple sets of communication modules, that is redirector and transport modules are capable of installing the applications on the workstations over a computer network. Therefore, the availability and compatibility of the redirectors and transports at the workstations must be assured. After the installation plan object is built by the user of application objects and workstation objects, the attributes of the application objects are examined for the communication modules which may be used for installation of the applications on the workstations. Next, the validation process determines whether the communication modules are available during the installation process at the workstations.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: August 11, 1998
    Assignee: International Business Machine Corporation
    Inventors: Theodore Jack London Shrader, John Lawrence Bunce, Diane Louise Skeel, George Edward Dever, Jr.
  • Patent number: 5793978
    Abstract: A method and system for routing packets, in which the resources consumed by broadcast packets are limited. Broadcast packets are placed in a separate queue that is managed independently of the buffer interface queue for non-broadcast packets. The broadcast queue is limited to a selected amount of communication bandwidth; when the amount of broadcast traffic exceeds the selected bandwidth, broadcast messages are queued and held for transmission until later (i.e., when the selected amount of bandwidth becomes available). An operator may specify a maximum number of broadcast packets to be sent in any one second period, an a maximum number of broadcast packet bytes to be sent in any one second period.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: August 11, 1998
    Assignee: Cisco Technology, Inc.
    Inventor: Gregory Alan Fowler
  • Patent number: 5790891
    Abstract: A data transfer synchronizing unit is provided for generating flags indicating the fullness state of a data transfer element. The determining unit includes the first and second counters operating according to first and second clock signals, first and second registers, serially connected to the output of the second counter, a latch unit and a comparator. The first register is clocked by the second clock signal and the second register is clocked by the first clock signal. The latch unit alternately activates the first and second registers to receive data in accordance with the second and first clock signals, respectively. The comparator produces the flags by comparing the output of the first counter with the output of the second register.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: August 4, 1998
    Assignee: Galileo Technology Ltd.
    Inventors: Yosef Solt, Doron Shefert, David Shemla, Eyal Waldman
  • Patent number: 5790791
    Abstract: A method and apparatus for choosing which flight management computer (FMC) of two FMCs will function as a master FMC (11) and which will function as a spare FMC (13) in maintaining data commonalty and synchronization between the master FMC (11) and the spare FMC (13) is disclosed. The status of a control switch (15) having FMC select and auto positions is scanned to determine the state of the switch. If the switch (15) is in an FMC select position, the related FMC is chosen to be the master FMC and the other FMC is chosen to be the spare FMC. If the switch is in the auto position, the failure status of the FMCs is evaluated. If one of the FMCs has failed, the other is chosen to be the master FMC. If the FMCs are both operating, the health of the FMCs is evaluated. If both FMCs are healthy, one is chosen to be the master FMC and the other is chosen to be the spare FMC, in accordance with a predetermined protocol. If the health of one of the FMCs has degraded, the other FMC is chosen to be the master FMC.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: August 4, 1998
    Assignee: The Boeing Company
    Inventors: Ray K. Chong, Peter D. Gunn, Richard A. Herald
  • Patent number: 5790896
    Abstract: An input/output module in a system for testing the functionality of an elronic system. The input/output module includes a plurality of input connections for receiving signals from the electronic system and a number of output connectors with different structural characteristics adapted for mating with plugs of correspondingly different structural characteristics to direct signals to another component of the testing system. For example the input/output module can include a plurality of BNC type plugs for signals of a first type and TNC type plugs for signals of a second type. This arrangement inhibits unintended cross connections between specific output connectors.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: August 4, 1998
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: John Thai Nguyen
  • Patent number: 5790892
    Abstract: An information handling system includes a number of processors, each connected to a processor bus, a memory controller connected to the processor bus which controls access to a system memory, a system controller, and one or more I/O controllers connected to the system bus where the system controller controls access to the system bus by all of the elements connected to the system bus, and the memory controller provides an efficient mechanism for handling data access to memory on read commands if a coherency response is modified. Combiner-prioritization logic in the memory controller includes logic in response to two additional inputs not shown in the prior art. The first logic responds to a read command and signals when a response window currently being combined is from a read command, and the second logic signals that the memory has an intervention buffer available to allow intervention.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: August 4, 1998
    Assignee: International Business Machines Corporation
    Inventors: John Michael Kaiser, Warren Edward Maule
  • Patent number: 5787307
    Abstract: Disclosed is an information processing apparatus which includes a processor, one or more input/output devices and an input/output bus for connecting the processor to the input/output devices. A bus connector is included for expanding the input/output bus to an external device. A first switch is used for electrically disconnecting bus signals that are carried by the input/output bus to corresponding connector pins of the bus connector. A second switch is used for electrically grounding the connector pins in the bus connector. The apparatus further includes switch control means for controlling the first and the second switches. When no external device is connected to the bus connector and the connector pins are exposed externally, the first switch is opened to cut off bus signals and to prevent the transmission of high frequency signals to the connector pins.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: July 28, 1998
    Assignee: International Business Machines Corporation
    Inventor: Naoyuki Imoto
  • Patent number: 5784570
    Abstract: The present invention relates to a server for further reducing the amount of information that needs to be sent from the server to a set of user devices associated with a multiuser interactive virtual environment. More specifically, a method of operation of a set of at least one server initially comprises receiving an input data stream representing a set of at least one characteristic of a first entity. The first entity inhabits a first location within the multiuser interactive virtual environment and is associated with a first user device. Next, the set of at least one server applies a recipient filter to the input data stream to identify a set of at least one user device that will be sent an output message. The output message represents the input data stream. The set of at least one user device comprises a second user device. The recipient filter is based upon the set of at least one characteristic. The second user device is associated with a second entity.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: July 21, 1998
    Assignee: AT&T Corp
    Inventor: Thomas A. Funkhouser