Abstract: With a gate electrode and side wall spacers being used as masks, ions of an n-type impurity are implanted from the normal line direction of a substrate, whereby source/drain diffused regions are formed. Then, ions of an n-type impurity are introduced by oblique implantation having a predetermined angle relative to the normal line direction of the substrate to form an n-type semiconductor region having an impurity concentration higher than source/drain extended regions. By this method, the junction depth of the semiconductor region becomes smaller than that of the source/drain diffused regions and greater than that of the source/drain extended regions.

Abstract: A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and instead of a dummy gate. Thereby, the SCR device has a narrower anode-to-cathode spacing, and then the lateral SCR device can be turned on more quickly to protect the CMOS IC's in ESD events. Additionally, the silicon area of the substrate occupied by the lateral SCR device is also saved. This method for forming a lateral SCR device without shallow-trench-isolation regions in its current path can be fully process-compatible to general CMOS technologies by only changing layout patterns in the mask layers.

Abstract: A substrate (110) for an unpackaged integrated circuit (IC) chip (118). The substrate comprises an insulative material (112), a plurality of contacts (114) disposed thereon, and a conductive ring (150) disposed around the outer perimeter of the contacts (114). Conductive traces (115) may be disposed around one or more contacts (114) and may be coupled to the conductive ring (150). An electro-less plating technique is utilized to plate contacts (114), avoiding unnecessary conductive material such as plating stubs being included in the contact (114) pattern, reducing interference. The conductive ring (150) shields the chip (118) from interference.

Abstract: A method for forming a multi-layer semiconductor device (1) having a lower silicon layer (4), an intermediate silicon layer (5) within which micro-mirrors (10) are formed and an upper spacer layer (6) of silicon for spacing another component from the micro-mirrors (10). First and second etch stop layers (8,9) of oxide act as insulation between the respective layers (4,5,6). In order to minimize damage to the micro-mirrors (10), the formation of the micro-mirrors (10) is left to the end of the forming process. An assembly of the lower layer (4) and the intermediate layer (5) with the first etch stop layer (8) is formed, and the second etch stop layer (9) is then grown and patterned on the intermediate layer (5) for subsequent formation of the micro-mirrors (10). The upper layer (5) is then bonded by an annealing process to the patterned second etch stop layer (9).

Abstract: An EEPROM device incorporates a partially encapsulated floating gate electrode in order to increase the capacitive coupling between the floating gate electrode and the control gate region of an EEPROM device. The floating gate electrode is partially encapsulated by a capacitor plate that is locally interconnected to the control gate region residing in a semiconductor substrate. The capacitor plate is electrically isolated from the floating gate electrode by a capacitor dielectric layer overlying the floating gate electrode. By partially encapsulating the floating gate electrode with a capacitor plate electrically connected to the control gate region, a high capacitance coupling is obtained between the floating gate electrode and the control gate region, while minimizing the substrate area necessary for fabrication of the capacitor portion of an EEPROM device.

Abstract: A semiconductor chip has a circuit block, a power supply line and a ground line. A condenser chip in which a noise reduction condenser connected to the circuit block is stacked on the semiconductor chip. Because the condenser chip is stacked on the semiconductor chip, it is not necessary to provide a noise reduction condenser on the semiconductor chip and also not to provide a noise reduction condenser on a substrate on which the semiconductor chip is mounted.

Abstract: An IGBT module comprises a ceramic substrate having a collector wiring element on a surface thereof, an IGBT chip provided on the collector wiring element, an insulative member provided on the collector wiring element and configured to cover at least edge portions of the IGBT chip, and an insulative sealing resin, provided on the ceramic substrate, for covering the IGBT chip and the insulative member. The sealing resin has lower insulation properties than the insulative member.

Abstract: The present invention provides for improved alignment of an opening in a lower dielectric layer with an opening in an upper dielectric layer. This improved alignment is beneficial as it improves the functionality of devices with dual damascene material arrangements, as normal misalignments do not deem the devices inferior or non-functional. Further, the present invention is beneficial as it allows for a designer, such as a microprocessor designer, to depend on more predictable conductive characteristics of contacts between a first conductive region and a second conductive region.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a substrate that has lattice points and interstitial points. The substrate includes a surface, a plurality pads located on the surface at interstitial points, and a plurality of vias located in the substrate only at lattice points.

Abstract: An integrated circuit device. The substrate includes a signal connection point and two shielding connection points set at the two sides of the signal connection point. The chip is set on the substrate. There are a signal pad and two shielding pads set at the two sides of the signal pad on the edge of the chip. The signal wire bonding is coupled to the signal connection point and the signal pad. Two shielding wire bondings are coupled to the shielding connection points and the shielding pads and extend along both sides of the signal wire bonding. The signal trace line is set on the substrate and coupled to the signal connection point. The power ring circuit is set on the substrate and coupled to the shielding connection points. The power circuit includes two shielding lines extending along both sides of the signal trace line.

Abstract: A semiconductor device has a gate electrode which is formed on a first conductive-type well set in semiconductor substrate, with a gate insulating film lying therebetween; a LDD structure in which, on either side of said gate electrode, there are formed a LDD region and a source/drain region; an interlayer insulating film to cover said gate electrode as well as said LDD regions; and contact sections. A contact section connecting to one side of the source/drain regions having a potential equal to a potential of said first conductive-type well is disposed so as to come into contact with the LDD region lying thereunder; and a contact section connecting to the other side of the source/drain region having a potential different from the potential of said first conductive-type well is disposed so as not to come into contact with the LDD region lying thereunder.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: The present invention relates to a method of manufacturing a thin film transistor in a semiconductor device. The present invention forms a single crystal silicon thin film on an interlayer insulating film on a single crystal driver transistor using a solid phase crystallization of amorphous silicon, forms a single crystal silicon thin film transistor (C—Si TFT) in the single crystal silicon thin film in order to uses it as a load transistor and uses a contact plug connecting a drain in the driver transistor and a drain in the load transistor as a SPC (solid phase crystallization) plug, in a process of depositing a silicon thin film on a single crystal transistor by a three-dimensional stack process to deposit to form a load transistor in a manufacture process of SRAM. Therefore, the present invention can improve the uniformity and reliability of the load transistor.

Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.

Abstract: A method used during the formation of a semiconductor device comprises forming a first portion of a digit line contact plug before forming storage capacitors. Subsequent to forming storage capacitors, a second portion of the digit line plug is formed to contact the first portion, then the digit line runner is formed to contact the second plug portion. A structure resulting from the process is also described.

Abstract: A semiconductor device, enabling reliable electrical connection of a main electrode pad with an interconnection pattern without separate provision of a via use electrode pad in addition to the existing main electrode pad, provided with a silicon substrate (semiconductor substrate), an electronic element formation layer formed on one surface of that silicon substrate, an electrode pad having an extension and electrically connected to the electronic element formation layer, a through hole passing through the electrode pad and the silicon substrate, an SiO2 film (insulating film), a via hole provided in the SiO2 film on the extension of the electrode pad, and an interconnection pattern electrically leading out the electrode pad to the other surface of the silicon substrate through the through hole and via hole, said through hole having a diameter larger at a portion passing through the electrode pad than a portion passing through the semiconductor substrate.

Abstract: The present invention relates to a method of packaging a microelectronic device that, in one embodiment, uses a vacuum-assisted underfill process. One embodiment of the method uses a curing process with a tacky film disposed over the device to prevent wicking of the underfill material after the underfill material is in place. One embodiment of the method uses a curing process that utilizes a non-tacky tacky film with a curing process to prevent wicking of the underfill material after the underfill material is in place.

Abstract: A semiconductor structure with common source line, the semiconductor structure has two word lines, some bit lines, a silicon-based layer and a suicide layer. The silicon-based layer is located between and electrically separated from these word lines, but is electrically coupled with these bit lines. The silicide layer is located over and electrically coupled with the silicon-based layer. Moreover, suicide layer and silicide layer could be replaced by a silicon-base conductor layer, and are directly electrically coupled with some separated doped regions that located inside a substrate.

Abstract: A downsized semiconductor device comprises a plurality of bonding pads formed on a surface of a semiconductor chip. A plurality of conductive wires are coupled to the bonding pad and extends away from the surface of the semiconductor chip. The surface of the semiconductor chip and the periphery of the plurality of conductive wires are covered with a resin layer. Each of the conductive wires and the resin layer covering the periphery of the conductive wire forms a coaxial body. A plurality of solder balls are mounted on the top end portion of the coaxial bodies and are electrically coupled with the conductive wires. Reinforcement resin portions are provided each of which is attached to an area from an upper end portion of the coaxial body to the solder ball to reinforce the coupling of the solder ball with the coaxial body.

Abstract: A semiconductor device includes: a wiring substrate; a wiring electrode; a semiconductor chip; a connecting member; and a resin encapsulant. The wiring electrode is formed on the wiring substrate. The semiconductor chip is mounted on the wiring substrate and a second bottom face of the semiconductor chip is in contact with the wiring substrate. An electrode pad formed on the semiconductor chip and the wiring electrode are electrically connected to each other with the connecting member. The semiconductor chip, the wiring electrode, and the connecting member, for example, are molded with the resin encapsulant on the upper surface of the wiring substrate. A level difference exists between a first bottom face and the second bottom face of the semiconductor chip. The first and second bottom faces are respectively located at a peripheral portion and a central portion of the semiconductor chip. A part of the resin encapsulant is interposed between the first bottom face and the upper surface of the wiring substrate.