Abstract: A lead end grid array semiconductor package comprises a leadframe having a plurality of leads. The leads extend outwardly from a chip paddle and have an outer end that defines an outer perimeter of the leadframe. A plurality of inner protrusions and outer protrusions are located on a lower surface of the leads. The outer protrusions communicate with the outer perimeter of the leadframe. An encapsulating material encapsulates the semiconductor chip and the conductive wires to form the semiconductor package. Solder balls are attached to a lower surface of the protrusions. The protrusions on the perimeter of the leadframe enable the semiconductor package to be positioned on a flat heat block when affixing the conductive wires to bond pads in the semiconductor chip. A ball of conductive material is affixed to the lower end of the protrusions to form a ball grid array.

Abstract: A semiconductor device is formed by including the step of forming a polycrystalline silicon layer on a semiconductor substrate which includes a pad oxide. A trench is formed in the semiconductor substrate by etching sequentially a part of the polycrystalline silicon layer, a part of the pad oxide layer, and a part of the semiconductor substrate. An oxide layer spacer is formed on the walls of the trench and the side walls of the etched pad oxide layer and the etched polycrystalline silicon layer. A nitride liner is formed on the oxide layer spacer. The trench is filled with an insulating layer on the nitride liner and the insulating layer is planarized until the polycrystalline silicon layer is exposed. And then the polycrystalline silicon layer is dry-etched.

Abstract: A transit time device (15, 15′) in a silicon-on-insulator (SOI) technology is disclosed. An anode region (18) and a cathode region (20) are formed on opposing ends of an epitaxial layer (14), with an intrinsic or lightly-doped region (22) disposed therebetween. Sinker structures (30p, 30n) are formed in an overlying epitaxial layer (24) over and in contact with the anode and cathode regions (18, 20). A charge injection terminal may be formed in a sinker structure (32n) in the overlying epitaxial layer (24), if the transit time device (15′) is of the three-terminal type. The device (15, 15′) has extremely low parasitic capacitance to substrate, because of the buried oxide layer (12) underlying the intrinsic region (22).

Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Abstract: A molded electronic component has numerous connection pins protruding on a single plane from a side surface area of an essentially cuboid housing, and a circumferential ridge of molded housing material protrudes from the other side area surfaces on the plane of the connection pins. The thickness of this ridge essentially corresponds to the thickness of the connection pins. On the side surface area located opposite the side surface area from which the connection pins protrude, in the plane of the connection pins, the ridge passes or transitions into a groove such that there is no ridge protruding outwardly beyond the side surface in this area. Thus, the component can be better placed by a tool such as a suction needle onto a printed circuit board without interference from such a ridge. The invention is particularly suitable for the production of molded electronic components whose separation plane runs through that housing surface which serves as a docking surface for a suction needle.

Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Therefore, the present invention can obtain an effect such as using a SOI substrate or a SIMOX substrate and can prevent a lowering in an electrical characteristic of the device, by using a bulk substrate made of a single crystal silicon but forming an insulating layer into which oxygen is injected below a LDD region.

Abstract: A power semiconductor package is provided. The power semiconductor package includes a chip, leads, conductive media, and a molding material. The leads have a groove in the shape of a hemisphere or a down-set. The package further includes an adhesive. The package can increase solder joint reliability and thermal performance. Also, the size of the package can be reduced, and sawing can be performed so that a burr does not occur.

Abstract: A field-effect semiconductor device, for example a MOSFET of the trench-gate type, comprises side-by-side device cells at a surface (10a) of a semiconductor body (10), and at least one drain connection (41) that extends in a drain trench (40) from the body surface (10a) to an underlying drain region (14a). A channel-accommodating region (15) of the device extends laterally to the drain trench (40). The drain trench (40) extends through the thickness of the channel-accommodating region (15) to the underlying drain region (14a), and the drain connection (41) is separated from the channel-accommodating region (15) by an intermediate insulating layer (24) on side-walls of the drain trench (40). A compact cellular layout can be achieved, with a significant proportion of the total cellular layout area accommodating conduction channels (12). The configuration in a discrete device avoids a need to use a substrate conduction path and so advantageously reduces the ON resistance of the device.

Abstract: A flip chip die, having a chip with an active surface, a passivation layer, at least one first bump pad and at least one second bump pad. The passivation layer, the first and second bump pads are formed on the active surface, where the first and second bump pads are exposed. The flip chip further has at least one first under ball metallurgy and one second under ball metallurgy formed on the first and the second bump pads, respectively. The contact area between the second under ball metallurgy and the second bump pad is larger than that between the first under ball metallurgy and the first bump pad. In addition, the flip chip has at least one first bump and at least one second bump formed on the first and second under ball metallurgies, respectively.

Abstract: A method of modeling delays in an integrated circuit design is disclosed that may be used to reduce the computation time of path delays in an integrated circuit design. A method of modeling delays in an integrated circuit design includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.

Abstract: A process for selectively sealing ferroelectric capacitive elements in non-volatile memory cells being integrated in a semiconductor substrate and comprising at least one MOS transistor, which process comprises at least the following steps: forming said at least one MOS transistor on the semiconductor substrate, and depositing an insulating layer over the whole surface of the semiconductor; and further comprises the steps of: depositing a first metal layer to form, using a photolithographic technique, a lower electrode of at least one ferroelectric capacitive element; depositing a layer of a dielectric material onto said first layer; depositing a second metal layer to form, using a photolithographic technique, an upper electrode of at least one ferroelectric capacitive element; depositing a layer of a sealing material onto said second metal layer; defining the dielectric material layer and sealing layer by a single photolithographic defining step, so as to pattern said dielectric layer and concurrently seal s

Abstract: An integrated circuit packaging assembly for reducing the length of bond wires transmitting radio frequency signals is disclosed herein. The die is offset in the packaging to position a subset of its bond pads in close proximity to package bond pads to allow for shorter bond wires, which reduces the inductive reactance that is induced in longer wires by high frequency signals. The subset of the bond pads is used for RF transmissions, while the other bond pads are used for direct current and low frequency signals.

Abstract: A damascene capacitor structure includes a recessed capacitor plate for preventing leakage and dielectric breakdown between the capacitor plates of the capacitor structure on the surface of the trenches and in the bottom corners of the trenches.

Abstract: An integrated circuit device is disclosed. The device includes an active film having a semiconducting material and an integrated circuit disposed on an active face of the active film. The integrated circuit includes a plurality of circuit elements. In addition, the device includes an additional film fixed to the active face of the active film, the additional film at least partially covering said integrated circuit, and an anti-fraud mechanism disposed within the additional film, the anti-fraud mechanism being positioned to align with one of the plurality of circuit elements. In some aspects, the additional film includes a protective sub-film and a sealing sub-film, wherein the protective sub-film is sealed to the active face of the active film by the sealing sub-film.

Abstract: Quasi-coaxial transmission lines to be “crossed” (over) are fabricated on a substrate. There are two cases: a true ground plane of metal will cover the substrate, or, each quasi-coaxial transmission line will have its own separate meandering bottom-half ground shield. In either case, when the crossed quasi-coaxial transmission lines are complete they will have top-half ground shields connected to metal against the substrate that is ground. If there is no ground plane the “crossing” quasi-coaxial transmission line that is to cross over must now have its bottom-half ground shield applied. It can overlay any top-half ground shield for any crossed quasi-coaxial transmission line that is in its path. If there is a ground plane, then that step is not necessary. Now a bottom-half layer of KQ dielectric material is applied along the path of the crossing quasi-coaxial transmission line. To this layer of KQ dielectric material is applied a layer of metal that becomes the center conductor.

Abstract: A method of forming fine patterns in a semiconductor device through a double photo lithography process. A layer to be etched and a hard mask layer are sequentially formed on a semiconductor substrate. A first photo resist pattern is formed on the hard mask layer. A first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After the first photo resist pattern is removed, a second photo resist pattern is formed on the resultant structure. A second hard mask layer pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. The layer to be etched is then etched using the second hard mask layer pattern after the second photo resist pattern has been removed, resulting in patterns have line edges without rounding.

Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

Abstract: A multi-layer conductor system including: a base layer having an electrically insulative top portion including alumina; an electrically conductive intermediate layer formed on the top portion of the base layer; and an electrically conductive top layer formed on the intermediate layer; wherein the intermediate layer includes alumina and a precious metal alloy consisting of silver and a precious metal other than silver; wherein the top layer comprises a precious metal selected from the group consisting of silver and a silver alloy such that the difference between the percentage weight of silver in the precious metal of the top layer and the percentage weight of silver in the precious metal alloy of the intermediate layer is limited to thereby provide advantages in use.

Abstract: In a TEG area, a conductive layer for a storage node is electrically connected through an impurity region positioned beneath the layer to an aluminum interconnection layer. In this manner, a test signal for checking a short circuit is given from the aluminum interconnection layer through a leading interconnection layer, the impurity region and so on to the storage node conductive layer. As a result, it is possible to obtain a semiconductor device making it possible to detect a short circuit between storage nodes stably even if the shape of the storage nodes in memory cells is made cylindrical; and a process for producing the same.