Abstract: An organic light emitting display device comprises a common voltage line formed over a peripheral region of a substrate; a passivation layer formed over a pixel region of the substrate and the peripheral region; pixel electrodes formed over the pixel region; and a pixel defining layer formed over the pixel region and the peripheral region. The pixel defining layer defines pixel openings overlapping the pixel electrodes, respectively. The device further comprises organic light emitting layers formed over the pixel region, and disposed in the pixel openings and over the pixel electrodes, respectively; and a common electrode formed over the pixel and peripheral regions. The common electrode is disposed over the pixel defining layer and the organic light emitting layers. The common electrode contacts the common voltage line. The passivation layer comprises a portion overlapping the common voltage line but not overlapping the pixel defining layer.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress.

Abstract: An organic electroluminescent display panel, a fabrication method thereof, and a display device are provided. The organic electroluminescent display panel includes: a base substrate and a package cover plate disposed opposite to each other, and an organic electroluminescent structure disposed on the base substrate and provided between the base substrate and the package cover plate. The package cover plate has a first groove for accommodating the organic electroluminescent structure within a display region of the organic electroluminescent display panel; the package cover plate has at least one second groove surrounding the first groove and having a closed boundary within a non-display region of the organic electroluminescent display panel; the second groove accommodates a sealant; and a metal layer is located between a protrusion portion of the package cover plate and the base substrate.

Abstract: Polaritonic hot electron infrared photodetector that detect infrared radiation. In one implementation, the polaritonic hot electron infrared photodetector includes a first contact layer, a second contact layer, a first dielectric layer, a second dielectric layer, and a conductor layer. The first dielectric layer is coupled between the first contact layer and the second contact layer. The second dielectric layer is coupled between the first dielectric layer and the second contact layer. The conductor layer is coupled between the first dielectric layer and the second dielectric layer. Infrared radiation incident upon the conductor layer is operable to create hot carriers that are injected from a conduction band of the conductor layer to a conduction band of the second contact layer.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density. The first insulation film is disposed in a lowest layer of the passivation film, the lowest layer being nearest to the semiconductor substrate. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.

Abstract: An optical device includes a carrier including a light transmitting layer and a light shielding layer disposed on the light transmitting layer. The optical device further includes a light emitter disposed on the carrier and a light detector disposed on the carrier. The optical device further includes a light transmitting encapsulant encapsulating the light emitter and the light detector, and a light shielding wall disposed in the light transmitting encapsulant and in contact with the light transmitting encapsulant and the light shielding layer.

Abstract: Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

Abstract: Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures within the region. The first-metal structure layout shapes are positioned on a first-metal vertical grid having at least eight first-metal gridlines. At least six contact structures are formed from substantially rectangular shaped contact structure layout shapes in physical and electrical contact with corresponding ones of at least six of the gate structures. A total number of first-transistor-type-only gate structures equals a total number of second-transistor-type-only gate structures within the region.

Abstract: An array substrate, a manufacturing method thereof and a display device. The array substrate includes a base substrate; and gate lines and data lines disposed on the base substrate, in which the gate lines and the data lines are intersected to define pixel regions; thin-film transistors (TFTs) are disposed in the pixel regions; a color filter layer is disposed on the TFTs; the color filter layer includes: single-primary color resist sections disposed in the pixel regions and multi-primary color resist sections disposed in light-shielding regions; the single-primary color resist sections each include a color resist layer of one primary color; and the multi-primary color resist sections each include color resist layers to shield light. Thus, color filters can be formed on the array substrate, the number of patterning processes can be reduced, and the production cost can be lowered.

Abstract: A circuit board comprises a mother substrate including first and second scribing regions, the first scribing region extending in first direction, the second scribing region extending in second direction, the first and second directions crossing each other, the mother substrate including chip regions defined by the first and second scribing regions, and a through via penetrating the chip regions of the mother substrate. The mother substrate comprises a first alignment pattern protruding from a top surface of the mother substrate. The first alignment pattern is disposed on at least one of the scribing regions.

Abstract: Methods for forming nanoporous semiconductor materials are described. The methods allow for the formation of micron-scale arrays of sub-10 nm nanopores in semiconductor materials with narrow size distributions and aspect ratios of over 400:1.

Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: An array substrate and a manufacturing method. The array substrate includes a substrate, multiple gate and data lines, and multiple common electrode lines parallel with the gate lines. The substrate includes a first surface. Among two adjacent gate lines and data lines, one pixel region is defined. The array substrate further includes a thin-film transistor, a common electrode, a pixel electrode and a storage capacitor disposed in the pixel region. The transistor includes a gate electrode, the first insulation layer, a channel layer, a source and drain electrode. The storage capacitor includes a first and a second conductive portion. The gate electrode, the common electrode line, the common electrode and the first conductive portion are disposed on the first surface. The channel layer, the source and drain electrode, the second conductive portion and the pixel electrode are disposed on the first insulation layer. The pixel electrode is a metal layer.

Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

Abstract: A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, and includes a first word line portion and a second word line portion. The second word line portion of the word line includes a first conductive oxide material. The bit line is disposed in a second direction perpendicular to the first direction. The nonvolatile memory material includes a barrier oxide material layer and a second conductive oxide material layer, with the barrier oxide material layer disposed adjacent the second word line portion of the word line.

Abstract: A quantum dot light emitting element includes a substrate, a cathode arranged on the substrate for supplying electrons, an electron injection/electron transport layer, a quantum dot light emitting layer, a hole injection/hole transport layer, and an anode for supplying holes. The cathode and the anode are arranged on the same side of the substrate. The electron injection/electron transport layer, the quantum dot light emitting layer, and the hole injection/hole transport layer are inserted between the cathode and the anode. One side of the electron injection/electron transport layer is connected to the cathode. The electron injection/electron transport layer and hole injection/hole transport layer are used for transmitting the electrons and the holes to the quantum dot light emitting layer, respectively. The electrons and the holes recombine in the quantum dot light emitting layer for emitting light. The electron injection/electron transport layer comprises a water-alcohol soluble conjugated polymer (WACPs).

Abstract: A sealing member containing conductive particles and disposed in a seal region is formed between a display panel and a touch panel. A laminated structure formed on the display panel includes a first detection lines. The first detection lines extend from the seal region to a connection region and are connected through the conductive particles to terminals of second detection lines formed on the touch panel. A peripheral edge of the organic barrier is located inward from the conductive particles of the sealing member. The above described structure can facilitate a work for connecting external lines such as FPC to the display panel and the touch panel. Further, the structure can secure stability of electrical connection between the external lines and the touch panel.

Abstract: A reticle may be fabricated and inspected. The reticle, which may include thin patterns, may be selectively incorporated into a fabricated semiconductor device based on measurement information generated based on the inspecting. The inspecting may include forming thin patterns on a substrate, forming a first discharge layer on the thin patterns, and directing a first charged particle beam to the substrate, such that the first charged particle beam passes through the first discharge layer. Measurement information may be generated based on the first charged particle beam. The first discharge layer may connect the thin patterns to each other and may be separated from the substrate between the thin patterns.

Abstract: A transparent display device includes a display substrate having a display region and a sealing region surrounding the display region. The display region includes a plurality of pixel regions, each of which includes a light-emitting region and a transparent region. An opposite substrate faces the display substrate. A sealing member is interposed between the display substrate and the opposite substrate. The sealing member overlaps the sealing region. The sealing member bonds the display substrate to the opposite substrate and includes a plurality of first light openings defined therein.