Patents Examined by Quoc Hoang
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Patent number: 10090378Abstract: Capacitors and methods of forming the same include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.Type: GrantFiled: March 17, 2017Date of Patent: October 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann A. M. Mignot, Hao Tang
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Patent number: 10084094Abstract: Semiconductor device and methods of forming the same include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer. The semiconductor fin is recessed below a height of the first and second dielectric layers. Source and drain extensions are grown from the recessed semiconductor fin. The first dielectric layer is recessed to expose an underside of and sidewalls of the source/drain extensions. Conductive contacts are formed around exposed portions of the source/drain extensions.Type: GrantFiled: March 17, 2017Date of Patent: September 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Zuoguang Liu, Heng Wu, Peng Xu
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Patent number: 10074743Abstract: A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess. The transverse spacing between the mesas and the lateral spacing between the mesas and an outer perimeter of a recess forming the mesas are substantially the same. A shield structure within the trench extends from the region between the mesas to the region between the ends of the mesas and the outer perimeter of the recess forming the mesas. A contact resides between a shield electrode terminal and the shield portion residing in the trench.Type: GrantFiled: May 25, 2017Date of Patent: September 11, 2018Assignee: NXP USA, Inc.Inventors: Ganming Qin, Edouard D. De Fresart, Pon Sung Ku, Michael F. Petras, Moaniss Zitouni, Dragan Zupac
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Patent number: 10074712Abstract: A display device includes, on a substrate, light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer including a light emission layer, and a second electrode layer and arranged in first and second directions which cross each other, a drive circuit including drive elements that drive light emitting elements, and a wiring extending in the first direction, and an insulating layer disposed in a gap region sandwiched by the light emitting elements neighboring in the second direction and having a recess or a projection. The wiring is disposed in an overlap region overlapping with the recess or the projection in the insulating layer in a thickness direction, in the gap region, and the second electrode layers in the light emitting elements neighboring in the second direction are separated from each other by the recess or the projection in the insulating layer.Type: GrantFiled: October 26, 2017Date of Patent: September 11, 2018Assignee: Sony CorporationInventor: Hiroshi Sagawa
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Patent number: 10067498Abstract: An apparatus is provided for generating electrical signals for stimulating a system under test (SUT). The apparatus comprises: a remote control panel configured to receive programming values and output programming signals; and a function generator. The function generator comprises: a communication port configured to receive the programming signals from the control panel; a memory configured to store instructions and predetermined values; a processor configured to process the programming signals and predetermined values according to the instructions stored in the memory; a digital-to-analog converter (DAC) configured to convert the processed signals into analog output signals; an output port configured to make the analog output signals available to the SUT; and an input port configured to receive second signals from the SUT.Type: GrantFiled: November 13, 2015Date of Patent: September 4, 2018Inventor: Harold T. Fogg
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Patent number: 10068880Abstract: It is an object of the present invention to provide a power module which can withstand a high voltage with a thin insulating layer.Type: GrantFiled: June 8, 2015Date of Patent: September 4, 2018Assignee: Hitachi Automotive Systems, Ltd.Inventors: Nobutake Tsuyuno, Junpei Kusukawa, Takeshi Tokuyama, Tokihito Suwa
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Patent number: 10064272Abstract: A light emitting device includes a light source, a light source carrier and a circuit board. The circuit board is configured to provide power to the light source via the light source carrier. The circuit board includes a metal substrate having an upper surface, the upper surface including a first electrode area, a second electrode area and a heat conduction area; a first metal electrode formed on the first electrode area; a first insulation layer formed between the first metal electrode and the metal substrate; a second metal electrode formed on the second electrode area; a second insulation layer formed between the second metal electrode and the metal substrate; and a solder resist layer covering the upper surface of the metal substrate; wherein the heat conduction area is exposed from the solder resist layer, and the heat conduction area is connected to the light source carrier.Type: GrantFiled: October 23, 2017Date of Patent: August 28, 2018Assignee: GENESIS PHOTONICS INC.Inventors: Hao-Chung Lee, Yu-Feng Lin, Meng-Ting Tsai
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Patent number: 10062715Abstract: A TFT array substrate and its manufacturing method are disclosed. The TFT array substrate includes a substrate having a display area and a non-display area, and at least a Schottky diode on the non-display area. The Schottky diode includes an anode layer and a cathode layer on the substrate, a gate insulation layer on the substrate covering the anode and cathode layers, a first gate on the gate insulation layer covering portions of the anode and cathode layers, an inter-layer insulation layer on the gate insulation layer covering the first gate and having a number of vias exposing the anode and cathode layers, respectively, and a first electrode and a second electrode in the vias on the inter-layer insulation layer connecting the anode and cathode layers, respectively. The present disclosure achieves simplified manufacturing process and reduced cost by forming the Schottky diode simultaneously when the TFT is formed.Type: GrantFiled: October 10, 2016Date of Patent: August 28, 2018Assignee: Wuhan China Star Optoelectronics Technology Co., LtdInventors: Lulu Xie, Bin Xiong, Yun Han
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Patent number: 10064252Abstract: An organic EL display unit includes a first substrate, a second substrate, a display layer, and a sealing section. The display layer is provided between the first substrate and the second substrate. The display layer includes an organic layer. The sealing section is provided continuously from an end surface of the display layer to at least a portion of respective end surfaces of the first substrate and the second substrate.Type: GrantFiled: September 14, 2015Date of Patent: August 28, 2018Assignee: Sony CorporationInventors: Keishi Tada, Jiro Yamada, Shinichiro Morikawa, Masaaki Sekine, Naoki Matsushita, Kohji Hanawa
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Patent number: 10057688Abstract: Systems and methods for lead frame-based chip carriers for use with MEMS transducers. One embodiment provides a method for manufacturing a MEMS microphone package. In one exemplary embodiment, the method includes flip chip bonding a first plurality of I/O pads on an application specific integrated circuit to a plurality of traces on a lead frame. The method further includes removing at least one of the plurality of traces such that at least one of the first plurality of I/O pads is electrically isolated from the lead frame. The method further includes bonding the lead frame to a lid and electrically connecting, via at least one wire bond, a MEMS microphone mounted to the lid to the application specific integrated circuit using a second plurality of I/O pads of the application specific integrated circuit. The method further includes bonding a substrate to the lead frame to form an air tight volume within the lid.Type: GrantFiled: November 3, 2015Date of Patent: August 21, 2018Assignee: Robert Bosch GmbHInventor: Jay Scott Salmon
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Patent number: 10056429Abstract: An optoelectronic device includes a first optoelectronic unit; a second optoelectronic unit; a third optoelectronic unit formed between the first optoelectronic unit and the second optoelectronic unit; a first electrode formed on and electrically connected to the first optoelectronic unit; a second electrode formed on and electrically connected to the second optoelectronic unit; a first pad electrically insulated from the third optoelectronic unit wherein the first pad is formed on the third optoelectronic unit or disposed between the first electrode and the second electrode; and a plurality of conductor arrangement structures electrically connected to the first optoelectronic unit, the second optoelectronic unit, and the third optoelectronic unit.Type: GrantFiled: August 7, 2017Date of Patent: August 21, 2018Assignee: EPISTAR CORPORATIONInventors: Chao Hsing Chen, Jia Kuen Wang, Chien Fu Shen, Chun Teng Ko
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Patent number: 10050093Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a stretchable substrate, a unit pixel over the stretchable substrate and including a plurality of emission layers emitting red light, green light, and blue light separately, and a plurality of interconnection lines connected to a corner portion of the unit pixel. The unit pixel has at least four corners, and the interconnection lines are respectively connected to the four corners.Type: GrantFiled: June 30, 2017Date of Patent: August 14, 2018Assignee: Samsung Display Co., Ltd.Inventors: Minjae Jeong, Gyungsoon Park, Jongho Hong
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Patent number: 10049891Abstract: Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents. The methods may also include contacting an exposed region of cobalt with the plasma effluents. The methods may include flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber. The methods may further include contacting the cobalt chloride with the nitrogen-containing precursor. The methods may also include recessing the cobalt, which leaves a residue behind. The methods may include forming a remote plasma of a hydrogen-containing precursor. The methods may also include removing the cobalt residue using plasma effluents of the hydrogen-containing precursor.Type: GrantFiled: May 31, 2017Date of Patent: August 14, 2018Assignee: Applied Materials, Inc.Inventors: Xikun Wang, Nitin Ingle
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Patent number: 10050220Abstract: The present invention provides a quantum dot light emitting element, a manufacture method thereof and a liquid crystal display device. The quantum dot light emitting element comprises a substrate, an anode, a Hole Injection and Hole Transporting Layer, a quantum dot light emitting layer, an Electron Injection and Electron Transporting layer and a cathode, and the anode is located on the substrate, and the anode and the cathode are located at the same side of the substrate, and are opposite and separately located, and the Hole Injection and Hole Transporting Layer, the quantum dot light emitting layer and the Electron Injection and Electron Transporting layer are sequentially sandwiched between the anode and the cathode, and one surface of the Hole Injection and Hole Transporting Layer is connected with the anode, wherein the Electron Injection and Electron Transporting layer comprises water/alcohol soluble conjugated polymer.Type: GrantFiled: February 18, 2016Date of Patent: August 14, 2018Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Chao Xu
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Patent number: 10042335Abstract: An emulation module configured to model a logical behavior of an industrial control device may be stored or embedded in the industrial control device for subsequent downloading and emulation by another device. The industrial control device storing the emulation module may execute firmware for its operation, and the stored emulation module may be used to model the logical behavior of the industrial control device executing the firmware. The industrial control device storing the emulation module may provide the emulation module to another device using an industry standard bi-directional communication interface, such as an EtherNet/IP control network interface. The industrial control device may also store multiple emulation modules with identifiable revisions, and a revision of an emulation module may correspond to a revision of firmware for execution by the industrial control device.Type: GrantFiled: January 20, 2016Date of Patent: August 7, 2018Assignee: Rockwell Automation Technologies, Inc.Inventor: Richard J. Grgic
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Patent number: 10044331Abstract: An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.Type: GrantFiled: June 7, 2016Date of Patent: August 7, 2018Assignee: Newport Fab, LLCInventors: Paul D. Hurwitz, Roda Kanawati
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Patent number: 10037964Abstract: A die-packaging component includes a substrate, a die, a jumper structure, a lead structure and a package body. The substrate has a base surface further including a die-connecting portion and a package-body retaining structure surrounding the die-connecting portion. The die connects the die-connecting portion. The jumper structure welded to the die generates a thermal deformation while in conducting a high-voltage current. The lead structure includes a lead groove defining a thermal-deformation tolerance allowable route. While in meeting the thermal deformation, the jumper structure welded to the lead groove as well is movable along the thermal-deformation tolerance allowable route. The package body at least partly covers the lead structure and the substrate, completely covers the die and the jumper structure, and is constrained by the package-body retaining structure.Type: GrantFiled: July 7, 2017Date of Patent: July 31, 2018Assignee: TAIWAN SEMICONDUCTOR CO., LTD.Inventors: Reyn Qin, Lucy Fan, Meifang Song, Xiaoli Wang
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Patent number: 10032758Abstract: According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.Type: GrantFiled: September 6, 2016Date of Patent: July 24, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura, Fumitaka Ishibashi
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Patent number: 10026753Abstract: A method includes providing a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region. A semiconductor device is provided in the SOI region. The semiconductor device includes a gate structure, a diode structure provided in the hybrid region and coupled to a substrate material of the SOI region, a supply circuit arrangement including first and second supply lines, a first resistor coupled between the first supply line and a first terminal of the diode structure, and a second resistor coupled between the second supply line and the substrate material positioned beneath the gate structure. At least one of the first and second resistors comprises a tunable resistor. A resistance of the tunable resistor is adjusted so as to adjust a threshold voltage (Vt) of the semiconductor device in dependence on an operating temperature of the SOI region.Type: GrantFiled: October 31, 2017Date of Patent: July 17, 2018Assignee: GLOBALFOUNDRIES Inc.Inventor: Juergen Faul
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Patent number: 10020463Abstract: A display device includes a first substrate, a light emitting element located on the first substrate and including a pair of electrodes and one organic layer or a plurality of organic layers located between the pair of electrodes, a second substrate located to face the first substrate, a third substrate located on a surface of the second substrate opposite to a surface thereof facing the light emitting element, and a tacky layer located between the second substrate and the third substrate, a tack strength between the tacky layer and the second substrate or the third substrate being weaker than an adhesive strength between one of the pair of electrodes and the one organic layer or an adhesive strength between the plurality of organic layers.Type: GrantFiled: June 22, 2017Date of Patent: July 10, 2018Assignee: Japan Display Inc.Inventor: Tetsuya Nagata