Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

Abstract: A display panel and the method of manufacturing the same, includes a first substrate disposed relatively to a second substrate, disposed above the first substrate. A black matrix, a poly silicon layer, a gate layer and a source drain layer disposed successively on the first substrate along direction facing the second substrate. The black matrix shelters the surrounding light which is incident from the first substrate onto the poly crystal layer, and the gate layer and the source-drain layer shelter the backlight which is incident from the second substrate onto the poly crystal layer. The manufacturing method of the display panel of the present invention could be simplified by the method described above.

Abstract: A display device includes, on a substrate, light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer including a light emission layer, and a second electrode layer and arranged in first and second directions which cross each other, a drive circuit including drive elements that drive light emitting elements, and a wiring extending in the first direction, and an insulating layer disposed in a gap region sandwiched by the light emitting elements neighboring in the second direction and having a recess or a projection. The wiring is disposed in an overlap region overlapping with the recess or the projection in the insulating layer in a thickness direction, in the gap region, and the second electrode layers in the light emitting elements neighboring in the second direction are separated from each other by the recess or the projection in the insulating layer.

Abstract: The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure.

Abstract: A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.

Abstract: A display panel is disclosed, which includes: a first substrate; a first metal line disposed above the first substrate and having a first surface and a first side, wherein the first side connects to the first surface, and the first side has a concave shape; and a sealant unit in contact with the first metal line, wherein the first metal line includes a first metal layer, a second metal layer and a third metal layer, the second metal layer locates between the first metal layer and the third metal layer, the sealant covers at least a portion of the first metal layer, and a part of the sealant locates between the first metal layer and the third metal layer.

Abstract: Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

Abstract: An array substrate and an LCD device are provided. The array substrate includes multiple LTPS thin-film transistors. Each transistor includes: a substrate; and a LTPS layer, a first insulation layer, a gate electrode, a second insulation layer, a source electrode, a drain electrode, a planarization layer, a first transparent conductive layer, a third insulation layer, a second transparent conductive layer and a connection metal layer. The LTPS layer, and gate electrode and the second insulation layer are sequentially disposed. The source electrode and the drain electrode are disposed on the second insulation layer, and connected with two terminals of the LTPS layer through the first and second through holes. The connection metal layer connects with the second transparent conductive layer and the drain electrode through a fourth through hole. The first transparent conductive layer is a common electrode and the second transparent conductive layer is a pixel electrode.

Abstract: A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

Abstract: A display apparatus includes a substrate. A display unit is disposed on the substrate and includes a display region and a non-display region. At least one light-emitting device is disposed in the display region. First and second power supply lines, configured to supply driving power to the at least one light-emitting device, and a pad unit, are disposed in the non-display region. The first power supply line includes a first fan-out wire portion electrically connected to the pad unit, and a first extension portion electrically connected to the first fan-out wire portion. The second power supply line includes a second fan-out wire portion electrically connected to the pad unit, and a second extension portion electrically connected to the second fan-out wire portion. The first extension portion has a width W1 and the second extension portion has a width W2. The width W1 is greater than the width W2.

Abstract: An organic light emitting device is provided. The organic light emitting device has a mixed light extraction layer, a base substrate, a first light extraction layer, a light-emitting layer, and a second light extraction layer; the first light extraction layer is configured to transmit the light emitted from the light-emitting layer to the base substrate; and the mixed light extraction layer is configured to transmit the emitting light outputted from the base substrate to an air area on the mixed light extraction layer, so as to increase a light utilization of the light-emitting layer.

Abstract: A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a higher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.

Abstract: A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.

Abstract: A sealing member containing conductive particles and disposed in a seal region is formed between a display panel and a touch panel. A laminated structure formed on the display panel includes a first detection lines. The first detection lines extend from the seal region to a connection region and are connected through the conductive particles to terminals of second detection lines formed on the touch panel. A peripheral edge of the organic barrier is located inward from the conductive particles of the sealing member. The above described structure can facilitate a work for connecting external lines such as FPC to the display panel and the touch panel. Further, the structure can secure stability of electrical connection between the external lines and the touch panel.

Abstract: According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers have a plurality of terrace portions arranged in a stairstep configuration with a difference in levels. The insulating layer is provided above the terrace portions. The columnar portions extend in a stacking direction of the stacked body through the insulating layer and through the stacked body under the insulating layer. The columnar portions are insulative. The contact portions are provided at side surfaces of the columnar portions on the terrace portions. The contact portions are connected to the terrace portions.

Abstract: 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

Abstract: Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about 275° C. The as-formed silicon nitride is exposed to a plasma. The silicon nitride may be formed as a portion of silicon nitride and at least one other portion of silicon nitride. The portion of silicon nitride and the at least one other portion of silicon nitride may be exposed to a plasma treatment. Methods of forming a semiconductor structure are also disclosed, as are semiconductor structures and silicon precursors.

Abstract: A display device is provided. The display device includes a first substrate; a first transistor and a second transistor disposed over the first substrate; a common electrode disposed over the first substrate; and a light-emitting diode chip (LED chip) disposed over the first substrate and disposed corresponding to the first transistor and the second transistor. The light-emitting diode chip includes a first light-emitting unit and a second light-emitting unit, wherein the first light-emitting unit is electrically connected to the first transistor and the common electrode, and the second light-emitting unit is electrically connected to the second transistor and the common electrode.

Abstract: A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

Abstract: A display may have an active area with an array of pixels to display images. An inactive area in the display may be formed from an opening in the active area. The inactive area may be enclosed by the pixels in the active area. An inactive border may run along an edge of the inactive area. A grid of positive power supply lines may be used to supply power to the pixels. Initialization voltage lines may be used to distribute initialization voltages to the pixels for use during transistor threshold voltage compensation operations. The inactive border may be free of positive power supply lines and initialization voltages lines. Control signal lines and data lines may pass through the inactive border to supply control signals and data signals respectively to the pixels. The display may have thin-film transistor circuitry with multiple layers of data lines.