Abstract: A semiconductor device includes a first compound semiconductor material, a second compound semiconductor material on the first compound semiconductor material, the second compound semiconductor material having a first doping concentration and including a different material than the first compound semiconductor material, a control electrode, and at least one buried semiconductor material region having a second doping concentration different from the first doping concentration. The at least one buried semiconductor material region is disposed in the second compound semiconductor material in a region other than a region of the second compound semiconductor material being covered by the control electrode.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor with peninsular ground contacts includes (a) a substrate having a plurality of pixel units arranged in rows of pixel units and (b) a plurality of ground contacts for grounding the pixel units, wherein the ground contacts are formed in respective peninsular regions of the substrate within respective ones of the pixel units, and wherein each of the peninsular regions is only partly enclosed by a shallow trench isolation and the peninsular regions have alternating orientation along each of the rows of pixel units.

Abstract: An integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion of especial utility in conjunction with magnetoresistive random access memory (MRAM) and other devices requiring magnetic shielding.

Abstract: Dual-Port SRAM cells are described. In an embodiment, a cell includes first and second pull-down, first and second pull-up, and first through fourth pass-gate transistors. Each transistor includes a first source/drain region in an active area, a channel extending above the active area, and a second source/drain region above the channel. First source/drain regions of pull-down transistors are electrically coupled through a first active area. First source/drain regions of pull-up transistors are electrically coupled through a second active area. A first, and a second, gate electrode is around channels of the first, and second, pull-down and pull-up transistors, respectively. Second source/drain regions of the first pull-down, first pull-up, and first and third pass-gate transistors are electrically coupled to the second gate electrode. Second source/drain regions of the second pull-down, second pull-up, and second and fourth pass-gate transistors are electrically coupled to the first gate electrode.

Abstract: A display screen and a method of preparing the same are disclosed. The method includes steps of: forming a flexible base layer (20) on a rigid base substrate (10), wherein the rigid base substrate (10) includes a first region (101), a second region (102), and a connection region (103) between the first region and the second region, and the flexible base layer (20) is at least formed in both the second region (102) and the connection region (103); fabricating an organic light emitting diode device on the substrate with the flexible base layer (20) formed thereon; and stripping the rigid base substrate (10) in the second region (102) along a boundary between the second region (102) and the connection region (103). By means of a flexible display technology, the above method can achieve seamless assembly between adjacent sub-screens, and therefore increases display quality of pictures.

Abstract: A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a precursor gas. The precursor gas adsorbed on a dielectric layer exposed by defects in a barrier layer is transformed to an insulating metal oxide layer, and the precursor gas adsorbed on the barrier layer is transformed to a metal layer.

Abstract: A display panel is disclosed, which comprises: a first substrate; a first metal line disposed on the first substrate and having a first surface and a first side connecting to the first surface, wherein the first side has a concave shape; and a sealant unit covering the first surface and the first side.

Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.

Abstract: A semiconductor device includes a resin package, a semiconductor chip sealed in the package and having first and second pads on a front surface. An island of the device has a projecting terminal sealed in the package, to one surface of which a back surface of the chip is bonded, and the other surface of which is partially exposed from a bottom surface of the package as a first terminal. A lead separate from the island is sealed in the package and has one surface electrically connected with the second pad, and another surface exposed from the package bottom surface as a second terminal capable of electrical connection between the second pad and outside. A mass center of the chip is away from a center of the package, the projecting terminal is as large as the lead, and solder under the device spreads to the island projecting terminal.

Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.

Abstract: The process of fabricating a flexible TFT back-panel includes depositing etch stop material on a glass support. A matrix of contact pads, gate electrodes and gate dielectric are deposited overlying the etch stop material. Vias are formed through the dielectric in communication with each pad. A matrix of TFTs is formed by depositing and patterning metal oxide semiconductor material to form an active layer of each TFT overlying the gate electrode. Source/drain metal is deposited on the active layer and in the vias in contact with the pads, the source/drain metal defining source/drain terminals of each TFT. Passivation material is deposited in overlying relationship to the TFTs. A color filter layer is formed on the passivation material and a flexible plastic carrier is affixed to the color filter. The glass support member and the etch stop material are then etched away to expose a surface of each of the pads.

Abstract: One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer.

Abstract: A display device includes, on a substrate, light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer including a light emission layer, and a second electrode layer and arranged in first and second directions which cross each other, a drive circuit including drive elements that drive light emitting elements, and a wiring extending in the first direction, and an insulating layer disposed in a gap region sandwiched by the light emitting elements neighboring in the second direction and having a recess or a projection. The wiring is disposed in an overlap region overlapping with the recess or the projection in the insulating layer in a thickness direction, in the gap region, and the second electrode layers in the light emitting elements neighboring in the second direction are separated from each other by the recess or the projection in the insulating layer.

Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Abstract: A method of forming an RRAM cell structure is provided. The method includes forming dummy features over a substrate, and the dummy features have a gap therebetween. The method also includes depositing an oxide layer over the dummy features while forming a first V-shaped valley on the oxide layer. The method further includes partially planarizing the oxide layer while leaving the first V-shaped valley. In addition, the method includes forming a first electrode over the oxide layer while forming a second V-shaped valley on the first electrode. The method further includes forming a resistance variable layer over the first electrode in a conformal manner. The method still includes forming a second electrode over the resistance variable layer.

Abstract: An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 ?m to 3.0 ?m inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Abstract: An organic light emitting display device comprises a common voltage line formed over a peripheral region of a substrate; a passivation layer formed over a pixel region of the substrate and the peripheral region; pixel electrodes formed over the pixel region; and a pixel defining layer formed over the pixel region and the peripheral region. The pixel defining layer defines pixel openings overlapping the pixel electrodes, respectively. The device further comprises organic light emitting layers formed over the pixel region, and disposed in the pixel openings and over the pixel electrodes, respectively; and a common electrode formed over the pixel and peripheral regions. The common electrode is disposed over the pixel defining layer and the organic light emitting layers. The common electrode contacts the common voltage line. The passivation layer comprises a portion overlapping the common voltage line but not overlapping the pixel defining layer.

Abstract: Provided is an organic EL illumination panel substrate, and a manufacturing method therefor, that improves the manufacturing efficiency and reduces the cost for an organic EL illumination panel substrate and that is capable of achieving an organic EL illumination panel with superior yields and reliability. The organic EL illumination panel substrate has a light transmitting substrate (11), a transparent electrode (12) and an auxiliary electrode (13). The transparent electrode (12) is arranged on one face of the light transmitting substrate (11). The auxiliary electrode (13) is electrically connected to the transparent electrode (12). On the light transmitting substrate (11), there is an insulating layer (14) at a position corresponding to an electrode lead-out section for an upper electrode of an organic EL layer that is disposed facing the transparent electrode (12) and that constitutes the organic EL illumination panel.