Patents Examined by R. A. Ratliff
  • Patent number: 5138431
    Abstract: Where a lead frame or lead structure in a plastic or ceramic-type package is made of a ferromagnetic material, an electrically conducting non-ferromagnetic material is added to create a low-inductance path between a semiconductor die and the terminals of the package to reduce self-inductance in the package. To provide an effective low-inductance current path to the ferromagnetic lead frame, the cross-sectional dimensions of the non-ferromagnetic path is preferably no less than 50 microinches. Where the lead frame or lead structure is made from an electrically conducting non-ferromagnetic material, a ferromagnetic material is added to provide strength and rigidity to the lead frame or lead structure. The material added may be plated, spot plated, or cladded onto the starting material. The leads or terminals of a socket may be also be constructed in a similar manner to improve its wear-resistance and rigidity while maintaining a low self-inductance.
    Type: Grant
    Filed: January 31, 1990
    Date of Patent: August 11, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: Chin-Ching Huang, Ronald J. Molnar
  • Patent number: 5138277
    Abstract: A switched capacitor integrator is used within the feedback loop of an automatic gain control (AGC) circuit to provide a very long time constant (5 minutes or more) when the amplitude of the gain-controlled signal is within predetermined limits. The time constant is automatically and quickly changed to a much shorter value when the gain-controlled signal is outside the predetermined limits, thereby allowing the AGC circuit to rapidly bring the gain-controlled signal amplitude within the desired range between the predetermined limits. Time constants of orders of magnitude longer than those readily realized with prior art methods of long time-constant filtering are achieved.
    Type: Grant
    Filed: September 28, 1990
    Date of Patent: August 11, 1992
    Assignee: Hazeltine Corp.
    Inventors: Kermit H. Robinson, Daniel M. Seslar
  • Patent number: 5132595
    Abstract: A filament switch for a rapid start fluorescent lamp disconnects or reduces through phase modulation the heating current to a plurality of lamp filaments to save power. The switch uses a trigger in series with a voltage sensitive element and an impedance element, the switch being responsive to the difference between a lamp starting voltage and a lamp sustaining voltage for determining when and for how long the filaments are heated.
    Type: Grant
    Filed: June 21, 1990
    Date of Patent: July 21, 1992
    Assignee: Magnetek Universal Mfg. Co.
    Inventors: Robert A. Kulka, Frederick P. Bauer
  • Patent number: 5130665
    Abstract: An audio volume controller includes a variable gain amplifier which amplifies an audio signal and drives a sound transducer such as a loud speaker. A volume controller is responsive to the level of the audio signal to adjust the gain of the amplifier to maintain the level of sound reproduced by the speaker between manually adjustable minimum and maximum values. A second minimum level control is provided to set a predetermined minimum audio signal level below which the gain of the amplifier is not increased in an attempt to maintain the sound level above the manually adjusted level.
    Type: Grant
    Filed: February 14, 1991
    Date of Patent: July 14, 1992
    Inventor: Richard L. Walden
  • Patent number: 5128627
    Abstract: A pulse power amplifier comprises a driver stage and a following splitter/combiner stage for symmetrical power division. The driver stage is preceded by a switch-over device in the signal path, the switch-over device also being connected to a decoupled port of the splitter/combiner stage via an additional signal path.
    Type: Grant
    Filed: February 15, 1991
    Date of Patent: July 7, 1992
    Assignee: Siemens Aktiengesellschaft
    Inventor: Peter Wendt
  • Patent number: 5126829
    Abstract: A cooling apparatus for an electronic device makes a cooling solid body in contact with the electronic device so as to cool the electronic device. The apparatus has a high viscous thermal conductive fluid provided on a heat transfer portion of the electronic device, and a cooling solid body in close contact through the thermal conductive fluid with the heat transfer portion of the electronic device. The close contact portion of at least one of the cooling solid body and the electronic device has multiple grooves open to the outside of the one of the cooling solid body and the electronic device.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: June 30, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Daikoku, Nobuo Kawasaki, Noriyuki Ashiwake, Shizuo Zushi
  • Patent number: 5122862
    Abstract: A ceramic lid for sealing a semiconductor element and having a sealing surface which is to seal a semiconductor element within a recess of a ceramic package, by heating the recess with glass sealant and hermetically sealing the semiconductor element. The ceramic lid is made of alumina of high purity and to the sealing surface of the ceramic lid is applied a glass sealing aid which is pretreated at a higher temperature than the heating temperature for sealing the semiconductor element, before hermetically sealing the semiconductor element in the ceramic package. A method of manufacturing a ceramic lid for sealing a semiconductor element includes the steps of manufacturing the ceramic lid with alumina of high purity having a sealing surface with the recess of the ceramic package, wherein to the sealing surface of the ceramic lid is applied a glass sealing aid of 5-30 .mu.m in thickness onto a sealing surface of the ceramic lid with the ceramic package.
    Type: Grant
    Filed: March 14, 1990
    Date of Patent: June 16, 1992
    Assignee: NGK Insulators, Ltd.
    Inventors: Takehiro Kajihara, Koichiro Maekawa, Toshio Ohashi
  • Patent number: 5118968
    Abstract: A special mode activation circuit is disclosed for activating a special mode circuit within a semiconductor integrated circuit when the voltage of an input signal at an input terminal of the integrated circuit reaches a special high voltage level that is substantially above a low voltage level range of signals normally associated with binary logic levels. The special mode activation circuit comprises a voltage reduction subcircuit, a voltage detection subcircuit, and an active pullup subcircuit. The voltage reduction subcircuit reduces the voltage of the input signal to generate a reduced voltage input signal. The voltage detection subcircuit is responsive to the reduced voltage signal to prevent activation of the special mode circuit when the reduced voltage input signal is less than a preset threshold value and to activate the special mode circuit when reduced voltage input signal exceeds the preset threshold value.
    Type: Grant
    Filed: September 12, 1990
    Date of Patent: June 2, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Kurt P. Douglas, Wen-Foo Chern, Vijaya B. Wickremarachchi
  • Patent number: 5117125
    Abstract: A logic level control circuit prevents impact ionization in a CMOS integrated circuit. The substrate bias voltage of the CMOS integrated circuit is detected by the control circuit and a control signal is provided in response to the detected bias voltage. The bias voltage can be zero volts or negative five volts. If the bias voltage is zero volts, the control signal is a logic level one. If the bias voltage is negative five volts, the control signal is a logic level zero. The control signal is applied to the gate of at least one other controlled device on the integrated circuit for turning the controlled device on and off. The controlled device coupled to a further CMOS device and turning the controlled device on and off prevents impact ionization by allowing the controlled device to alternately divide a voltage level with the further CMOS device or be effectively removed from the circuit.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: May 26, 1992
    Assignee: National Semiconductor Corp.
    Inventor: Michael K. Mayes
  • Patent number: 5117160
    Abstract: A phosphor layer is coated on an inner wall of a tubular glass bulb. A predetermined amount of a rare gas containing xenon gas as a main component thereof is sealed and enclosed in the tubular glass bulb. A pair of belt-shaped electrodes are formed on an outer wall of the enclosed glass bulb throughout substantially the entire length of the glass bulb.
    Type: Grant
    Filed: June 19, 1990
    Date of Patent: May 26, 1992
    Assignee: NEC Corporation
    Inventors: Tsutomu Konda, Seiichiro Fujioka, Satoshi Tamura, Osamu Matsubara, Shodo Yoshida
  • Patent number: 5111257
    Abstract: A non-volatile semiconductor memory device includes a substrate (1) having a plurality of element-forming regions (3), a plurality of recesses (32) located between the element-forming regions (3), and a plurality of element-isolating regions (31); word lines (8a to 8d); bit lines (10) orthogonal to this word lines; and memory cells (511) each formed at the point of intersection of these word and bit lines at each element-forming region (3). Each memory cell (511) includes an electrically floating electrode (5) in the form of a flat plate, a control gate electrode (7) in the form of a substantially flat plate formed on the floating gate electrode (5) and connected to the word lines (8a to 8d), and a pair of impurity regions (21, 23) formed respectively at opposite sides of the floating gate electrode (5) on the surface of a semiconductor substrate (1).
    Type: Grant
    Filed: December 14, 1989
    Date of Patent: May 5, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuaki Andoh, Osamu Ueda
  • Patent number: 5109268
    Abstract: An improved semiconductor package is provided wherein the mounting pad for the semiconductor is made from a material selected from the group consisting of aluminum nitride, diamond, alumina, and boron nitride.
    Type: Grant
    Filed: December 29, 1989
    Date of Patent: April 28, 1992
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Gasper A. Butera
  • Patent number: 5107319
    Abstract: A photodiode-FET combination having an optimized layer structure wherein the photodiode and the FET are separated from one another by a separating trench and are separated from the substrate by barrier layers forming a pn-junction in order to avoid tributary currents. A layer sequence is provided formed of an absorption layer grown on in surface-wide fashion, of a photodiode layer that is likewise grown on in surface-wide fashion and which is etched back to the region of light incidence in the region of the photodiode, of a channel layer in the region of the FET, and of a cover layer on the channel layer which forms a gate.
    Type: Grant
    Filed: May 25, 1990
    Date of Patent: April 21, 1992
    Assignee: Siemens Aktiengesellschaft
    Inventors: Christl Lauterbach, Helmut Albrecht
  • Patent number: 5105260
    Abstract: An improved transistor package with superior stability to wave soldering, having a nickel oxide barrier strip formed on the surface of the leads.
    Type: Grant
    Filed: October 31, 1989
    Date of Patent: April 14, 1992
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Gaspar A. Butera
  • Patent number: 5105127
    Abstract: A dimming device, with a brightness dimming ratio of 1 to 1000, for a fluorescent lamp used for the backlighting of a liquid crystal screen comprises a periodic signal generator for delivering rectangular pulses with an adjustable duty cycle. The pulses are synchronized with the image synchronizing signal of the liquid crystal screen. An alternating voltage generator provides power to the lamp only during the pulses. The decrease in tube efficiency for very short pulses allows the required dimming intensity to be achieved without image flickering.
    Type: Grant
    Filed: June 21, 1990
    Date of Patent: April 14, 1992
    Assignee: Thomson-CSF
    Inventors: Georges Lavaud, Jean P. Bouron
  • Patent number: 5103268
    Abstract: A semiconductor device having a thin film silicon-containing active layer and a metallic first electrode is provided with an interfacial metallic layer at an inner surface of a second electrode to increase electrical resistance and thereby reduce shunts adjacent pinhole-type defects of the active layer. The interfacial layer is preferably made of a metal selected from the group consisting of tin, gold, titanium, palladium and tantalum.
    Type: Grant
    Filed: July 8, 1991
    Date of Patent: April 7, 1992
    Assignee: Siemens Solar Industries, L.P.
    Inventors: Ming-Jau Yin, David P. Tanner
  • Patent number: 5095359
    Abstract: A semiconductor package for use in computers includes a insulating substrate onto which a semiconductor device is mounted, an insulating cap which shuts out outside air and seals said semiconductor device, power-source lines which provide power to the semiconductor device, and signal lines which transmit output signals from the semiconductor device to external circuits. The signal lines are arranged perpendicularly to the insulating substrate so that they are prevented from the dielectric constant of the insulating substrate, while the power-source lines are formed within the insulating substrate and connected through conductive layers parallel to the surface onto which the semiconductor is mounted to external leads.
    Type: Grant
    Filed: September 28, 1989
    Date of Patent: March 10, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Akira Tanaka, Hirokazu Inoue, Kazuji Yamada, Kunio Miyazaki, Osamu Miura, Hideo Arakawa, Hiroshi Yokoyama, Yoshio Naganuma, Atsushi Morihara, Katsunori Ouchi
  • Patent number: 5093713
    Abstract: A semiconductor device package includes a first semiconductor chip. The first semiconductor chip is mounted on a substrate island region. A lead frame is arranged to serve as an external terminal of the first semiconductor chip, and includes an island region for mounting at least one second semiconductor chip.
    Type: Grant
    Filed: May 8, 1991
    Date of Patent: March 3, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiromichi Sawaya
  • Patent number: 5093711
    Abstract: A semiconductor device used as an electrically programmable read-only memory. The resistance of the device is irreversibly varied from a high value to a low value by applying an electric field. The device is composed of a silicon semiconductor substrate of a first conductivity type, a diffused layer of a second conductivity type opposite to the first conductivity type, an interlayer insulating film formed on the diffused layer, an amorphous silicon layer containing impurity of the first conductivity type, and a metal film forming conductive interconnections. The diffused layer acts as a lower electrode. The metal film serves as an upper electrode. The amorphous silicon layer and the metal film are stacked on the diffused layer.
    Type: Grant
    Filed: October 11, 1989
    Date of Patent: March 3, 1992
    Assignee: Seiko Epson Corporation
    Inventor: Kazuki Hirakawa
  • Patent number: 5087963
    Abstract: In a glass-sealed semiconductor device, low-melting glass is glazed on a ceramic base to fix a lead frame. A distal end portion of the lead frame, the distal end portion being connected to a semiconductor element, is fixed to the ceramic base through devitrifying glass layer.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: February 11, 1992
    Assignee: NEC Corporation
    Inventors: Kenichi Kaneda, Akio Tanda