Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns, clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: A system, may include a processor configured to receive circuit design data, identify one or more critical paths of the circuit design data, and generate one or more synthetic tunable replica circuits (STRCs) that may mimic the one or more critical paths. The processor may then compile the circuit design data and the one or more STRCs into program data. The system may also include an integrated circuit including a control circuit that may receive the program data from the processor, program a plurality of programmable logic regions of the integrated circuit to implement the circuit design data and the one or more STRCs, and adjust one or more operating parameters of at least one of the plurality of programmable logic regions based on the one or more STRCs.

Abstract: The disclosed multi-level driving data transmission circuit and operating method include: a first driving module including a first signal generating unit and a first three-state driver, and a second driving module, including a second three-state driver. The first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver. The first signal generating unit includes a first and second input terminals, and an output terminal. The output terminal of the first signal generating unit couples to the second input terminal of the first three-state driver. The first signal generating unit receives the first signal through its first input terminal and the first feedback signal of the first signal from the second driving module through its second input terminal. The resultant first control signal has an effective signal width wider than the first signal. The first control signal inputs to the first three-state driver.

Abstract: A transmitter includes a driving circuitry configured to drive a channel coupled to an output node by controlling an output impedance of a pull-up path, an output impedance of a pull-down path, or both, according to one or more multi-bit data signals, a pull-up control signal, and a pull-down control signal; a driving control circuit configured to generate the pull-up control signal and the pull-down control signal according to one or more calibration signals and the multi-bit data signals or according to the calibration signals and one or more duplicate multi-bit data signals, the duplicate multi-bit data signals duplicating the multi-bit data signals; and a look-up table storing values of the calibration signals.

Abstract: Novel and useful electronic and magnetic control of several quantum structures that provide various control functions. An electric field provides control and is created by a voltage applied to a control terminal. Alternatively, an inductor or resonator provides control. An electric field functions as the main control and an auxiliary magnetic field provides additional control on the control gate. The magnetic field is used to control different aspects of the quantum structure. The magnetic field impacts the spin of the electron by tending to align to the magnetic field. The Bloch sphere is a geometrical representation of the state of a two-level quantum system and defined by a vector in x, y, z spherical coordinates.

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: The present disclosure relates to a power control device, a driving module and a switching power supply device. The power control device includes: a control terminal, configured to input and output a control signal to and from the driving module; an enable output terminal, configured to output an enable signal to the driving module; a control circuit; and an input/output circuit, configured to have the control signal be a first logic level when the output transistor is turned on and the synchronous rectifier transistor is turned off, and to have the control signal be a second logic level when the output transistor is turned off and the synchronous rectifier transistor is turned on, and to be able to become an input standby state according to an instruction from the control circuit.

Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

Abstract: An integrated circuit may include an embedded test processor that is capable of performing in-field testing and repair of hardware-related defects without having to remove the integrated circuit from the customer's board. The test processor can be used to drive and monitor test vectors to performing defect screening on input-output circuitry, logic circuitry including lookup table (LUT) circuits and digital signal processing (DSP) circuits, transceiver circuitry, and configuration random-access memory circuitry. The test processor can generate a failure mechanism report and selectively fix repairable defects via a hardware redundancy scheme. The failure mechanism report allows the customer to identify the root cause of failure in the overall system.

Abstract: An adder with first and second majority gates is provided. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

Abstract: An encapsulated LED switch that incorporates a MOSFET power drivers, high current transistors, or other suitable power drivers in a PCB that attaches to the LED switch such that a low power LED switch controls the output of a high-power driver. The selected power driver PCB can be adapted to different load requirements by making simple changes. The PCB's can be interchanged to provide for a predetermined output power required for a particular application. In addition, the wire gauge size of the wires attached to the MOSFET power driver PCB can also be varied to match intended load requirements. For applications in which the LED switch is used in hostile environments, such as marine applications, the LED switch and its associated power driver PCB are encapsulated to protect the circuitry from environmental factors such as high humidity, salt water, etc.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

Abstract: A sensor fixed atop a structure. The sensor including an image-capturing device configured to collect image data, and an electronic processing device. The electronic processing device configured to receive, via the image-capturing device, the image data, determine a wobble state of the image data, perform a first timeout for a first predetermined time period when the wobble state is approximately equal to a wobble state level, and increment the first timeout to a second timeout for a second predetermined time period when the wobble state value is approximately equal to the wobble state level following the first timeout.

Abstract: A field-programmable gate array (FPGA) architecture capable of performing immutable hardware Root-of-Trust updates and patches. In embodiments, the architecture utilizes the dielectric breakdown mechanism of magneto tunnel junctions (MTJ) to operate both as: 1) multi-time programmable (MTP) configuration memory for reconfigurable FPGA designs, and 2) one-time programmable (OTP) memory for FPGA Root-of-Trust sections.

Abstract: According to one embodiment, a semiconductor device includes first, second, third, and fourth circuits. A first voltage is applied to the first circuit. A second voltage is applied to each of the second, third and fourth circuits. The third circuit is configured to generate a first control signal and a second control signal based on a signal generated by the first circuit and a signal generated by the second circuit. The fourth circuit is configured to output an output signal based on the first control signal and the second control signal. The output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied.

Abstract: A control device configured for use in a load control system to control an external electrical load may provide simple feedback regarding the operation of the control device. For example, the control device may comprise a base portion configured to be mounted to an electrical wallbox or over a mechanical switch, and a control unit connected to the base portion. The control unit may comprise a rotation portion rotatable with respect to the base portion, an actuation portion, and a light source. The control unit may be configured to control the light source to illuminate at least an illuminated portion of the actuation portion in response to actuations of the rotation portion and the actuation portion. In addition, the control unit may provide a limit indication on the illuminated portion by blinking the illuminated portion when the electrical load has reached a limit.

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.