Abstract: Methods, systems and apparatus for producing quantum circuits with low T gate counts. In one aspect, a method for performing a temporary logical AND operation on two control qubits includes the actions of obtaining an ancilla qubit in an A-state; computing a logical-AND of the two control qubits and storing the computed logical-AND in the state of the ancilla qubit, comprising replacing the A-state of the ancilla qubit with the logical-AND of the two control qubits; maintaining the ancilla qubit storing the logical-AND of the two controls until a first condition is satisfied; and erasing the ancilla qubit when the first condition is satisfied.

Abstract: Main wiring including a plurality of differential transmission lines for transmitting differential signals is formed on a motherboard. Termination resistors, provided at both ends of each of the plurality of differential transmission lines, connect the plurality of differential transmission lines to each other. A plurality of daughter boards are connected in parallel to each other via the main wiring. A line characteristic impedance of each differential transmission line is higher than a termination resistance value, which is a resistance value of the termination resistor.

Abstract: None of the existing quantum programming languages provide specialized support for programming patterns such as conditional-adjoint or adjoint-via-conjugation. As a result, compilers of these languages fail to exploit the optimization opportunities mentioned in this disclosure. Further, none of the available quantum programming languages provide support for automatic translation of circuits using clean qubits to circuits that use idle qubits. Thus, the resulting circuits oftentimes use more qubits than would be required. Embodiments of the disclosed technology, thus allow one to run said circuits on smaller quantum devices. Previous multiplication circuits make use of (expensive) controlled additions. Embodiments of the disclosed technology employ multipliers that work using conditional-adjoint additions, which are cheaper to implement on both near-term and large-scale quantum hardware. The savings lie between 1.5 and 2× in circuit depth for large number of qubits.

Abstract: A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

Abstract: A light-emitting circuit includes first and second light-emitting element strings respectively configured to emit light having a first and second color temperatures; a rectifying circuit configured to rectify a voltage, input by an alternating current (AC) power source, to generate a driving voltage; a string switching circuit configured to select at least one light-emitting element string to be used for light emission from among the first light-emitting element string and the second light-emitting element string; an off/on sensing circuit configured to change a selection of the string switching circuit to change a color temperature of light, which is emitted by the light-emitting circuit, when the AC power source is turned off and then turned on; and a driving circuit configured to turn on, in turn, light-emitting elements in the selected at least one light-emitting element string, according to a change in the driving voltage over time.

Abstract: A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: An encapsulated LED switch that incorporates a MOSFET power drivers, high current transistors, or other suitable power drivers in a PCB that attaches to the LED switch such that a low power LED switch controls the output of a high-power driver. The selected power driver PCB can be adapted to different load requirements by making simple changes. The PCB's can be interchanged to provide for a predetermined output power required for a particular application. In addition, the wire gauge size of the wires attached to the MOSFET power driver PCB can also be varied to match intended load requirements. For applications in which the LED switch is used in hostile environments, such as marine applications, the LED switch and its associated power driver PCB are encapsulated to protect the circuitry from environmental factors such as high humidity, salt water, etc.

Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.

Abstract: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Abstract: The present disclosure relates to a compiling method (50) for converting an input quantum circuit into an output quantum circuit compliant with predetermined constraints of a quantum computer, said input quantum circuit being composed of quantum gates to be applied to a set of qubits, said quantum gates arranged successively in an execution order, wherein said method comprises, for each quantum gate of the input quantum circuit processed according to the execution order: if the processed quantum gate corresponds to an operator of a set of synthesizable operators: (S53) update the synthesizable accumulated operator to include the operator corresponding to the quantum gate, otherwise: a) (S54) synthesize a partial quantum sub-circuit partially implementing the current synthesizable accumulated operator and modify accordingly the synthesizable accumulated operator, and b) (S55) append the partial quantum sub-circuit to the output quantum circuit.

Abstract: An airflow generation device having a first dielectric substrate made from a rubber elastic material, a first electrode on or near by a first surface of the first dielectric substrate, a second electrode on a second surface, and a second dielectric substrate made from a rubber elastic material covering the second electrode. It makes the airflows generated by plasma caused from partial gas near by the first surface through applied voltage into the first electrode and the second electrode, and bonding portions between the first electrode and the second electrode and the first dielectric substrate, bonding portions between the second electrode and the second dielectric substrate, and bonding portions between the first dielectric substrate and the second dielectric substrate are bonded by chemical bonds with chemically crosslinking.

Abstract: A device for synchronous serial data transmission over a differential data channel and a differential clock channel includes an interface controller having a clock generator, data controller, clock transmitter block and data receiver block. The clock generator generates a transmit clock signal which, during a data transmission cycle, includes a clock pulse train having a period. The clock generator is suitably configured such that, for data transmission cycles in a dynamic operating state in which a maximum occurring differential voltage of a differential clock signal is lower than a maximum differential voltage of the clock transmitter block, the clock generator sets a duration of a first clock phase of a first clock period of the clock pulse train to be longer than a first clock phase of following clock periods and shorter than a time duration required to reach the maximum differential voltage.

Abstract: A hybrid quantum-classical computing method for solving optimization problems though applications of non-unitary transformations. An initial state is prepared, a transformation is applied, and the state is updated to provide an improved answer. This update procedure is iterated until convergence to an approximately optimal solution.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Abstract: A method of detecting cliques in a graph includes determining, based on a number of nodes in the graph, a number of qubits to be included in a quantum processor. The method includes assigning to each node in the graph, a qubit of the quantum processor. The method includes operating on the qubits with a preparation circuit to create a quantum state in the qubits that corresponds to the graph. The method includes operating on the quantum state with a random walk circuit, and measuring the qubits of the quantum processor to detect cliques in the graph. The preparation circuit comprises a plurality of single- and two-qubit operators, wherein, for each pair of adjacent nodes in the graph, an operator of the plurality of two-qubit operators acts on a pair of qubits corresponding to the pair of adjacent nodes to create the quantum state.

Abstract: A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.

Abstract: Techniques for providing hardware-efficient fault-tolerant quantum operations are provided. In some aspects a cavity and an ancilla transmon are used to implement a quantum operation by encoding a logical qubit using more than two energy levels of the cavity, encoding information using more than two energy levels of the ancilla transmon, and creating an interaction between the cavity and the ancilla transmon that decouples at least one error type in the ancilla transmon from the cavity.