Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: The network device may be configured to define or update a scene for controlling a zone in a certain area or location of a load control system. For example, the load control system may be installed in a residential home or building. At least one lighting control device that is configured to control a corresponding lighting load may be assigned to each of the one or more zones. The network device may be configured to display one or more graphical user interfaces that a user of the network device may interact with to define or update a scene. The network device may also be configured to display one or more graphical user interfaces that a user of the network device may interact with to define or update natural show functionality. After a scene and/or natural show have been configured, the may enabled or activated in response to a triggering event.

Abstract: A quantum computing system implementing surface code in a measurement circuit may be configured to translate a quantum algorithm including at least one Hadamard gate into an equivalent circuit that lacks a Hadamard gate, the circuit including Hadamard-conjugated Pauli measurements that include joint logical measurements implemented on diagonally-arranged patches of the surface code.

Abstract: A method for implementing a multiplier on a programmable logic device (PLD) is disclosed. Partial product bits of the multiplier are identified and how the partial product bits are to be summed to generate a final product from a multiplier and multiplicand are determined. Chains of PLD cells and cells in the chains of PLD cells for generating and summing the partial product bits are assigned. It is determined whether a bit in an assigned cell in an assigned chain of PLD cells is under-utilized. In response to determining that a bit is under-utilized, the assigning of the chains of PLD cells and cells for generating and summing the partial product bits are changed to improve an overall utilization of the chains of PLD cells and cells in the chains of PLD cells.

Abstract: The present disclosure relates to a reciprocal quantum logic (RQL) inverter including an inverter bias tap, a pulse generating Josephson junction (JJ), and a superconducting quantum interference device (SQUID) based structure, which includes a SQUID JJ and is connected between the inverter bias tap and the pulse generating JJ. The SQUID based structure is configured to receive an inverter bias signal from the inverter bias tap and receive a data input from a previous circuit stage. When the data input is at logic state “0,” the pulse generating JJ can be triggered so as to provide an output signal with logic state “1.” When the data input is at logic state “1,” the first SQUID JJ can be triggered thereby preventing the pulse generating JJ from be triggered, such that the output signal is provided at logic state “0.

Abstract: A plasma density monitor for monitoring a plasma density of surface wave plasma in a chamber accommodating a substrate and performs a plasma process on the substrate. The monitor includes: a monopole antenna installed to extend from a wall of the chamber toward an interior of the chamber and to be perpendicular to an inner wall surface of the chamber, and configured to receive a surface wave; a coaxial line configured to extract a detection value from a signal received by the monopole antenna; a length adjuster configured to adjust a length of the monopole antenna; and a controller configured to control the length adjuster so as to obtain a wavelength of the surface wave and the plasma density of the surface wave plasma from the wavelength of the surface wave.

Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.

Abstract: Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a logic circuit. A pre-emphasis control signal based on at least one of the pull-up and pull-down data activation signals is provided to control providing pre-emphasis having a timing based on a mode of operation.

Abstract: An integrated circuit is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the integrated circuit and other similarly designed integrated circuit. These small differences can cause transistors of the integrated circuit to have different threshold voltages. The integrated circuit can use these different threshold voltages to quantify its physical uniqueness to differentiate itself from other integrated circuits similarly designed and fabricated by the semiconductor fabrication process.

Abstract: A semiconductor memory device has an output driving circuit. The output driving circuit includes a pull-down driver and a gate control logic. The pull-down driver includes first and second transistors. The first and second transistors are coupled between a pad and a ground node. The gate control logic includes third and fourth transistors. The third and fourth transistors are coupled between a pad and a first supply voltage node. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage. The first transistor is controlled by the feedback voltage. The second and third transistors are controlled by the first supply voltage. The fourth transistor is controlled by the voltage of the pad.

Abstract: A transmitter provides a duobinary signal corresponding to one of level 0, level 1, and level 2 based on first data and second data, and includes a pull-up driving circuit including a plurality of pull-up resistors selectively coupled between a first power source and a transmission node according to the first data and the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively coupled between the transmission node and a second power source, wherein at least one of the plurality of pull-up resistors is coupled between the first power source and the transmission node both when the first data is activated and when the second data is activated, or at least one of the plurality of pull-down resistors is coupled between the second power source and the transmission node both when the first data is activated and when the second data is activated.

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

Abstract: A logic circuit includes a first pull-up driving circuit configured to drive a first inverted input signal to a supply voltage based on a first input signal, and configured to pull up an output signal based on the first input signal, a second input signal, and a third inverted input signal. The logic circuit also includes a first pull-down driving circuit configured to drive the third inverted input signal to a ground voltage based on the third input signal, and configured to pull down the output signal based on the first inverted input signal, the second input signal, and the third input signal.

Abstract: Methods and apparatus provide plasma generation for semiconductor process chambers. In some embodiments, the plasma is generated by a system that may comprise a process chamber having at least two upper microwave cavities separated from a lower microwave cavity by a metallic plate with a plurality of radiation slots, at least one microwave input port connected to a first one of the at least two upper microwave cavities, at least two microwave input ports connected to a second one of the at least two upper microwave cavities, and the lower microwave cavity receives radiation through the plurality of radiation slots in the metallic plate from both of the at least two upper microwave cavities, the lower microwave cavity is configured to form an electric field that provides uniform plasma distribution in a process volume of the process chamber.

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Abstract: A controllable lighting device may utilize a controllable impedance circuit to conduct a load current through an LED light source. The controllable impedance circuit may be coupled in series with a first switching device, which may be rendered conductive and non-conductive via a pulse-width modulated signal to adjust an average magnitude of the load current. The controllable lighting device may further comprise a control loop circuit that includes a second switching device. The second switching device may be rendered conductive and non-conductive in coordination with the first switching device to control when a feedback signal is provided to the control loop circuit and used to control the LED light source. The control loop circuit may be characterized by a time constant that is significantly greater than an operating period of the load current.

Abstract: One example includes a pulse selector system. The pulse selector system includes an input Josephson transmission line (JTL) configured to propagate an input reciprocal quantum logic (RQL) pulse received at an input based on a bias signal. The RQL pulse includes a fluxon and an antifluxon. The system also includes an escape Josephson junction coupled to an output of the input JTL. The escape Josephson junction can be configured to pass a selected one of the fluxon and the antifluxon of the RQL pulse and to trigger in response to the other of the fluxon and the antifluxon of the RQL pulse to block the other of the fluxon and the antifluxon of the RQL pulse. The system further includes an output JTL configured to propagate the selected one of the fluxon and the antifluxon as a unipolar pulse to an output based on the bias signal.