Patents Examined by R. R. Kucia
  • Patent number: 4894751
    Abstract: An easily automated and heat-stable semiconductor contacting system for linear and planar SMD components, particularly LED arrangements. SMD components are applied to a carrier film coated with interconnects. The interconnects are entirely or partly formed of solderable material for simpler contacting through melting.
    Type: Grant
    Filed: May 20, 1988
    Date of Patent: January 16, 1990
    Assignee: Siemens Aktiengesellschaft
    Inventor: Ulrich Wehnelt
  • Patent number: 4888665
    Abstract: A customizable circuit using a programmable interconnect and a compatible tape design for tape automated bonding of chips to the circuitry. The programmable interconnect comprises layers of wires, with one layer of wires forming overlap regions with the adjacent layer of wires. The wires can be selectively linked later to form the desired interconnect. The selective linkage represents the customization of an otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed is a method for forming the interconnect.
    Type: Grant
    Filed: February 19, 1988
    Date of Patent: December 19, 1989
    Assignee: Microelectronics and Computer Technology Corporation
    Inventor: Lawrence N. Smith
  • Patent number: 4888450
    Abstract: Printed circuit boards having a plurality of circuit layers are produced using a specific processing sequence. A copper-clad substrate is first patterned in a desired configuration to produce the first layer of the printed circuit board. The patterned metallization is then covered with a specifically formalated energy sensitive material. The energy sensitive material is delineated in a desired pattern and developed to uncover portions of the underlying metallization pattern. The entire substrate is blanket-cured to produce a rigid layer having openings in appropriate places. The openings are metallized and a second copper pattern is produced on the cured polymer by conventional metallization and lithographic techniques. If desired, the process is repeated until a suitable number of copper patterned levels are obtained.
    Type: Grant
    Filed: June 28, 1985
    Date of Patent: December 19, 1989
    Assignee: AT&T Bell Laboratories
    Inventors: David J. Lando, Frederick R. Wight, Jr.
  • Patent number: 4885126
    Abstract: An electronic circuit component housing assembly adapted to be mounted mechanically on a printed circuit, using a single mechanical fastener to attach the circuit component housing assembly in a unique alignment with the printed circuit, and simultaneously using the fastener to provide force to press physically compliant electrical contacts included in the circuit component housing assembly into electrical contact with terminal contact pads on the printed circuit. Several electronic circuit components may be housed in separate hermetically sealed cavities and can be biased independently of one another. Thermal conductors are included in the base member and a convection cooler is mounted atop the assembly. The mechanical fastener also acts as a thermal conductor. A test probe assembly including multiple contacts mounts on the electronic circuit component housing.
    Type: Grant
    Filed: March 18, 1988
    Date of Patent: December 5, 1989
    Inventor: John D. Polonio
  • Patent number: 4883920
    Abstract: In the chip type component installation structure wherein chips are arranged to be joined by solder to a fitting pattern provided on a printed substrate, resist films are set separately in the space of the fitting pattern in order to reduce the quantity of solder. The resist films are set in the space of the fitting pattern separately, so that the structure provides a lesser quantity of solder to join and fix chips, a continuous solder band over the fitting pattern, and a lesser but sufficient quantity of the solder. The structure prevents cracks and breakages of chips due to the expansion and contraction of solder, increases the polarity of solder against chips and electrodes, shortens the soldering time, and increases the reliability of chip installation work.
    Type: Grant
    Filed: May 31, 1988
    Date of Patent: November 28, 1989
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takeshi Tanabe, Toshio Hori
  • Patent number: 4882455
    Abstract: An electronic circuit substrate having excellent machinability and dimensional accuracy is disclosed, which comprises a porous ceramic sintered body having a three-dimensional network structure and contains permeable pores, and a resin filled into the permeable pores.
    Type: Grant
    Filed: August 2, 1988
    Date of Patent: November 21, 1989
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasuyuki Sato, Shinji Saito, Hidetoshi Yamauchi
  • Patent number: 4878153
    Abstract: An electronic shelf assembly for holding a plurality of electronic modules. The shelf assembly has a first substantially flat, flexible, preformed plastic plate having a plurality of parallel guide channels defined by opposed parallel ribs projecting out of the plane of the first plate. The plate has a predetermined convex contour perpendicular to the guide channels. Small raised extensions in substantially the center of each of the guide channels project out of the plane of the first plate for engaging a recess in at least a first edge of the module, when the module is fully inserted in one of the guide channels. A second substantially flat, flexible, preformed plastic plate has a plurality of parallel guide channels defined by opposed parallel ribs projecting out of the plane of the second plate. The guide channels of the second plate are longitudinally aligned with respective ones of the guide channels of the first plate.
    Type: Grant
    Filed: May 23, 1988
    Date of Patent: October 31, 1989
    Assignee: Rockwell International Corporation
    Inventor: William P. Loris
  • Patent number: 4878155
    Abstract: Decoupling capacitance is provided with negligible inductance in a high speed discrete wire logic panel by the use of SMT (surface mounting) capacitors that are mounted in holes in the circuit board. A hole is formed in the circuit board under each location where a dual-in-line IC (integrated circuit) is to be mounted, and an SMT capacitor is mounted in the hole, with the opposite terminals of the capacitor soldered to the conductive layers on opposite board surfaces. Each quantity of solder extends substantially in the plane of a corresponding conductive layer. Only one side of each capacitor terminal is soldered to a conductive layer, to permit flux washout. In the PGA (pin grid array) area of the circuit board, a capacitor is selectively mounted under an IC by removing a pin from a hole lying under the pin-free area in the center of the IC, and installing a capacitor in the hole.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: October 31, 1989
    Inventor: Larry R. Conley
  • Patent number: 4876630
    Abstract: A mid-plane board for orthogonally interconnecting a first set of circuit boards to a second set of circuit boards. The mid-plane board has a first group of pins which project outwardly equally on both sides of the board. It has second and third groups of pins which project outwardly only on one or the other side of the mid-plane board, respectively. The circuit boards have edge connectors and the pins of the first, second and third groups are associated with the edge connectors in a manner such that the circuit boards of the first set are orthogonal to those of the second set when they are connected to the pins. An assembly for the mid-plane board and the circuit boards is also disclosed.
    Type: Grant
    Filed: September 23, 1988
    Date of Patent: October 24, 1989
    Assignee: Reliance Comm/Tec Corporation
    Inventor: Prithipal Dara
  • Patent number: 4875140
    Abstract: Support for printed circuit boards formed by a column (1) comprising at least one base (3) on which a printed circuit board (6) is to be supported, a collar (4) which is inserted in a hole (5) of the plate, a coupling member, a damper (7) being inserted between the base (3) and the circuit plate (6), the compression of the said damper being ensured by the coupling member.
    Type: Grant
    Filed: April 12, 1988
    Date of Patent: October 17, 1989
    Assignee: U.S. Philips Corporation
    Inventors: Guy Delpech, Gilles Garnier
  • Patent number: 4875138
    Abstract: The bond pads (22) for a ceramic package (10) are deposited on the pre-fired ceramic at variable pitch with the bond pad widths (47) increasing as a function of the distance (49) of each pad from an alignment point (40), whereby bond pads at the extremity (36) of the package have the largest pad width and pads toward the alignment point (40) of the package have the narrowest width.
    Type: Grant
    Filed: June 24, 1988
    Date of Patent: October 17, 1989
    Assignee: United Technologies Corporation
    Inventor: Michael D. Cusack
  • Patent number: 4873397
    Abstract: An electronic circuit element capable of positively and stably accomplishing its provisional fixing on a printed circuit board substantially free of any trouble and being readily taken out or extracted for the mounting on a printed circuit board, irrespective of a manner of holding of the circuit element prior to the extraction. The electronic circuit element includes an element body and an adhesive or polymeric layer deposited on the element body. The polymeric layer is arranged on a surface of the element body opposite to a printed circuit board on which the circuit element is to be mounted. The polymeric layer is formed of a material exhibiting adhesion when it is heated to a temperature of about 80.degree. C.
    Type: Grant
    Filed: December 28, 1987
    Date of Patent: October 10, 1989
    Assignee: TDK Corporation
    Inventors: Sho Masujima, Hiroshi Yagi, Atsuzo Tamashima, Jun Tamashima
  • Patent number: 4870225
    Abstract: A mounting arrangement of a chip type component onto a printed circuit board, which includes a chip type component having terminal electrodes at its opposite end portions, and land portions provided on a printed circuit board so as to fix the chip type component on them by soldering through cream type solder applied onto the land portions. The land portions are each formed to have such a length as will not project externally in a longitudinal direction of the chip type component.
    Type: Grant
    Filed: March 27, 1989
    Date of Patent: September 26, 1989
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kimiharu Anao, Yoshitsugu Hori, Keiichi Shimamaki, Tadashi Sato
  • Patent number: 4866571
    Abstract: A semiconductor package for mounting a chip is disclosed. The package includes a first metal or metal alloy component having a first thin refractory oxide layer on a first surface. The chip is bonded to the first component. A skirt extends from the first component for strengthening the first component and providing heat transfer from the semiconductor package. A second metal or metal alloy lead frame having second and third refractory oxide layers on opposite surfaces is electrically connected to the chip and is bonded to the first oxide layer. Also, the lead frame is insulated from the first component by the first and second refractory oxide layers. A second metal or metal alloy component has a fourth refractory oxide layer on one surface and is bonded to the third refractory oxide layer so that the chip is hermetically sealed between the first and second components.
    Type: Grant
    Filed: August 23, 1984
    Date of Patent: September 12, 1989
    Assignee: Olin Corporation
    Inventor: Sheldon H. Butt
  • Patent number: 4864079
    Abstract: A surface-mounted electrical component has rectangular section leads that project outwardly from the edges of the component body. The leads are bent down towards the surface of the substrate and are twisted through 90 degrees about their length to make the leads compliant in a direction transverse of their width where they emerge from the body. The lower end of the leads are straight and untwisted, making a vertical butt solder joint with contact pads on the substrate. The twisted region of the leads are treated, such as by nickel plating, to render them non-wetted by solder. Because of the greater spacing possible between the contact pads, conductive tracks can extend through gaps between the contact pads beneath the body of the component.
    Type: Grant
    Filed: March 9, 1988
    Date of Patent: September 5, 1989
    Assignee: Smiths Industries Public Limited Company
    Inventor: Alan Barlow
  • Patent number: 4862326
    Abstract: An electronic system which requires high current provides a connector assembly which enables power supplies to be plugged into the same etched backplane as the logic printed circuit boards. The connector assembly handles high current, typically 150 amps at 5V DC. A female connector includes sets of fingers which flex at the base of the fingers to provide a low resistance contact.
    Type: Grant
    Filed: April 12, 1988
    Date of Patent: August 29, 1989
    Assignee: BULL HN Information Systems Inc.
    Inventors: John W. Blomstedt, Wesley F. Irving, Mark S. Pusateri
  • Patent number: 4862327
    Abstract: In a low profile microcomputer, adapter cards are mounted horizontally in order to be able to use adapter cards designed for earlier, higher, machines. The cards are coupled to the microcomputer planar board by an extender card which extends vertically from the planar and has sockets extending horizontally when the card is in position. The adapter cards have edge connections which couple to these sockets. A removable bridge device is coupled between the top of the extender card and a vertical wall of the microcomputer to minimize horizontal movement of the extender card. For adapter cards which do not extend fully between the front and rear walls of the microcomputer, a channelled support arm, which fits over an end of a card, and is removably mounted on a vertical wall of the computer for slidable engagement with the card.
    Type: Grant
    Filed: June 9, 1988
    Date of Patent: August 29, 1989
    Assignee: International Business Machines Corporation
    Inventors: Daniel F. Ansell, James C. Harris, Steven E. Howell, Michael S. Miller, Robert D. Wysong
  • Patent number: 4861944
    Abstract: A pin grid array package includes an electrically insulating, moisture impervious base having a plurality of bores therethrough, electrically conducting pins extending through the bores, metallic collars wedged between the pins and the bores adjacent the bottom side of the base, an electrically conducting trace formed of a silver-2 percent platinum alloy extending from each pin to the location for attachment of an electrical device, and a melted eutectic bond between the metal of the conducting path and the head of the pin at the top side of the base.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: August 29, 1989
    Assignee: Cabot Electronics Ceramics, Inc.
    Inventors: Kenneth L. Jones, II, Tom R. O'Connor, Kenneth A. Trevellyan
  • Patent number: 4862323
    Abstract: A chip carrier and a process of assembling a chip carrier are disclosed. The carrier used for mounting a chip comprises a copper or copper base alloy component having a thin refractory oxide layer on a surface thereof. The surface and the oxide layer have an indentation formed therein for receiving the chip. A metallic circuit pattern for electrical connection to the chip is bonded to the oxide layer and insulated from the copper or copper base alloy by the refractory oxide layer. A seal is provided for enclosing the chip to the indentation. Another embodiment of the invention includes a circuit board structure comprising a circuit board device having a first coefficient of thermal expansion. A chip carrier is provided having a second coefficient thermal expansion of substantially the same value as the first coefficient of thermal expansion.
    Type: Grant
    Filed: May 22, 1985
    Date of Patent: August 29, 1989
    Assignee: Olin Corporation
    Inventor: Sheldon H. Butt
  • Patent number: 4862325
    Abstract: A printed wiring board is mounted with an electronic component which is provided with grooves at the opposite sides thereof. The grooves are constructed so that the electronic component can be mounted on the printed wiring board in either the vertical or horizontal directions. Preferably, the grooves have a cross-shaped configuration, one extending vertically and one extending horizontally. The grooves may be formed on tongue pieces projecting from the electronic component body. The groove may be provided with a resilient piece. Another groove may be provided on the body so as to be capable of changing the direction of terminals.
    Type: Grant
    Filed: December 17, 1987
    Date of Patent: August 29, 1989
    Assignee: Nihon Kaiheiki Kogyo Kabushiki Kaisha
    Inventor: Shigeo Ohashi