Abstract: Multi-layer circuitry incorporating electronic elements is disclosed. The circuitry comprises a plurality of layers including a metal or alloy substrate formed with a recess on one surface. An electronic element is positioned within the recess and a second electronic element is positioned on the surface. Also, a first dielectric material layer is disposed on the surface. Further, a first layered conductive circuit pattern overlies the first dielectric material layer so as to provide circuitry over a substantial portion of the substrate. The first circuit pattern is electrically connected to the first electronic element. The first circuit pattern also has a cavity therein for receiving the second electronic element. A second layered conductive pattern overlies at least a portion of the first layered conductive circuit pattern and the second electronic element and is electrically connected to the second electronic element.

Abstract: In connection with a method and a device for mounting electric components, such as coils, anti-interference coils, transformers, transistors, capacitors, or the like, on a circuit board, it is proposed to give the carrier housing for the electric component a two-part design and to lock the lower part directly on the printed circuit board, while an upper housing part serving as a component carrier may be locked in two different positions on the lower housing part.

Abstract: A substrate mounting device for installing an electrical substrate to a carrier substrate. The substrate mounting device includes a plurality of tabs extending from the perimeter edges of the electrical substrate. First and second substrate guides are mounted to the carrier substrate and each include a lower shelf and a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn from a plurality of slots. The electrical substrate is installed by manually inserting the electrical substrate into a respective substrate guide open end and manually pushing the electrical substrate along the channels until the electrical substrate encounters a respective top guide whereby, the electrical substrate is urged downward. Each tab then falls within a respective slot, resting the electrical substrate on the lower shelf.

Abstract: A ceramic multilayer circuit board comprising ceramic layers and wiring conductor layers laminated alternately, in which the ceramic layer has a thermal expansion coefficient lower than that of the wiring conductor and not lower than one half of that of the conductor layer and is formed from a glass which softens at a temperature not higher than the melting point of the wiring conductor layer; a semiconductor module having a high reliability in its solder joint part comprising said ceramic multilayer circuit board mounted with a ceramic carrier substrate being mounted with a semiconductor device, said board being able to use a silver or copper conductor having a good electro-conductivity; and an amorphous glass powder for said ceramic multilayer circuit board.

Abstract: A surface mounting method which utilizes an adhesive component to mount the electrical components to a printed circuit board instead of solder and which includes the use, between the contacting surfaces, of a flowable, corrosion-resistant material which bridges contact imperfections and penetrates surface films. The method may also be implemented to connect two electrical conductors.

Abstract: A method and structure are disclosed for mounting and connecting an electic device such as an integrated circuit to a circuit board. The board has a plurality of embedded shielded conductors for interconnecting the integrated circuit to other devices on the board. In order to limit the capacitance and inductance of the connection, the integrated circuit is mass bonded directly to the conductors and to their coaxial shields.

Abstract: A semiconductor device including interconnection lines for connecting element regions is disclosed. Each of interconnection lines is comprised of a first layer consisting essentially of aluminum, an alumina film formed on the first layer and a second layer containing silicon and deposited on the alumina film. Refractory metal silicide such as tungsten silicide, molybdenum silicide, titanium silicide, tantalum silicide and chrominum silicide is favorably employed as the second layer. Hillock formation and electromigration are thus prevented or suppressed.

Abstract: A printed circuit device including semiconductor IC chips on the surface of a printed circuit board made of insulating material. The printed circuit board includes on the surface thereof semiconductor mounting regions and conductive layers. The semiconductor IC chips are respectively fixedly mounted on the semiconductor element mounting regions disposed on the printed circuit board. Thin metal wires interconnect electrodes of the IC chips with the conductive layers. A sealing cover plate having a plurality of recesses formed therein is fixedly mounted onto the surface of the printed circuit board with adhesive for hermetically sealing each of the IC chips and electric wires with a respective one of the recesses in the cover plate. The cover plate can comprise a composite of a thermoplastic resin material layer and a metal layer, such as aluminum or an aluminum alloy.

Abstract: A multilayer printed circuit board in which multiple layers of a composite material, fabricated by the lay-up of an aramid fiber tape, are employed to provide a circuit board with a desired coefficient of thermal expansion. Tape lay-up of aramid fibers provides a composite layer having a lower thermal coefficient of expansion than a composite layer fabricated from woven aramid fibers. Degradation in the tensile modulus of elasticity caused by the over and under characteristics of woven fabrics is also eliminated by tape lay-up, thus providing a circuit board with better mechanical strength. In addition, tape lay-up reduces the amount of resin required to fabricate the circuit board and eliminates the need for twisting the aramid fibers into yarns and then weaving the yarns, thus reducing the cost of the circuit board.

Abstract: Engineering changes in the wiring between semiconductor device chips supported on the same substrate are made using minimum substrate real estate and without the use of engineering change pads or discrete wires by the use of easily modified chip interposers. The interposers are inserted between respective chips and the substrate. The interposers comprise conductive vias and multiple internal wiring planes which are selectively connected to the vias.

Abstract: An integrated (silicon based) packaging/wiring structure provides for VLSI chips 4 to be placed within openings of somewhat larger size in a semiconductor interconnection wafer (IW, 2) supported by a carrier 1. The interconnection wafer 2 includes multilevel (ML) wiring planes and incorporated circuit components integrated in a less demanding technology as compared to the VLSI chips 4. Silicon contact chips 5 with conductive surface layers 22, 23 placed over the chip/IW plane provide for the required interconnections by means of needle-like structures 24 inserted in corresponding via holes. The needles are better suited to withstand shear strain than are conventional C-4 (Controlled Collapse Chip Connection) joints. Consequently a much higher number of chip pads can be provided. Power supply is effected via rather large-dimensioned conductive planes, e.g.

Abstract: An apparatus for automatically analyzing gases in oil, wherein a gas analyzer analyzes the total quantity of combustible gases extracted from the oil or the quantities of several specified ones of the combustible gases, comprising a data processor determining the presence or absence of the abnormality of an oil-immersed equipment on the basis of the increasing or decreasing trend of the analyzed results obtained in several analyzing operations, or calculating the sampling period of oil sampling and analytical processing routines, on the basis of the increasing or decreasing trend of the analyzed results, whereby the abnormality can be automatically determined with a high reliability.

Abstract: A substrate mounting device for installing an electrical substrate to a carrier substrate. The substrate mounting device includes a plurality of guide rails mounted on the perimeter edge of the electrical substrate. First and second substrate guides are mounted to the carrier substrate in a spaced and parallel relationship to the other. Each substrate guide includes a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. The electrical substrate is installed by manually inserting the electrical substrate into respective substrate guide open ends and manually pushing the electrical substrate along the channels until the substrate encounters a respective top guide.

Abstract: A substrate mounting device for installing an electrical substrate to a carrier substrate. The substrate mounting device includes a plurality of guide rails mounted on the perimeter edge of the electrical substrate. First and second substrate guides are mounted to the carrier substrate in a spaced and parallel relationship to the other. Each substrate guide includes a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. The electrical substrate is installed by manually inserting the electrical substrate into respective substrate guide open ends and manually pushing the electrical substrate along the channels until the substrate encounters a respective top guide.

Abstract: A substrate mounting device for installing an electrical substrate to a carrier substrate. The substrate mounting device includes a plurality of tabs extending from the perimeter edges of the electrical substrate. First and second substrate guides are mounted to the carrier substrate and each include a lower shelf and a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. The electrical substrate is installed by manually inserting the electrical substrate into a respective substrate guide open end and manually pushing the electrical substrate along the channels until the electrical substrate encounters a respective top guide whereby, the electrical substrate is urged downward. Each tab then falls within a respective slot, resting the electrical substrate on the lower shelf.

Abstract: The invention is directed to a mount of a resiliently elastic, planar printed circuit board in a housing having a curved shape and composed of two parts. The end regions of the printed circuit board are secured such that a temporary positional change of the printed circuit board is impossible. This is achieved by having at least one resilient fastening element in the form of a shackle projecting from one of the housing parts overlaping the printed circuit board and/or pressing thereagainst in interlocking fashion at at least one end region of the printed circuit board. The shackle has a length such that the printed circuit board conforms to a shape adapted to the shape of the housing part accepting it.

Abstract: A method of forming double polysilicon contacts to underlying diffused regions of a semiconductor body which includes forming first and second level electrically conductive silicon layers over the body which contact respective first and second diffused regions of the body. The diffused regions are formed such that said first diffused region is ringed by said second diffused region. The second silicon layer thus overlaps the first silicon layer. The top surfaces of the first and second silicon layers are silicided such that the silicide formed over the first silicon layer is aligned with the edge of the second silicon layer.

Abstract: A wiring structure for a termination circuit in which a termination circuit is connected to an integrated circuit through a fixed wiring pattern provided in a leadout layer closest to the mounting surface.

Abstract: An improved test apparatus is disclosed for testing leadless IC chip carriers or IC dies. The apparatus employs a flexible film on which is imprinted a conductor line pattern terminated in a plurality of raised conductive pads. The line pattern is readily formed on the film surface using photolithographic techniques. The conductive pads are arranged on the film surface in such a way as to conform to the positioning of the edge contact terminals of the chip carrier. A frame structure is provided for resiliently urging the chip carrier against the surface of the film, with the edge terminals of the chip carrier in electrical contact with the raised pads on the film. The conductor lines on the film are also terminated in raised pads, which are urged against a printed wire pattern on a rigid circuit board, which provides connections to the chip carrier test equipment. Thus, electrical contact is made to the chip carrier without the use of wire bonds or solder connections.

Abstract: A method and apparatus for determining the oxygen uptake rate of bacteria in a body of liquid incorporates withdrawing a sample of the liquid into a chamber where a dissolved oxygen probe is located, the probe outputting a signal which is a function of the amount of dissolved oxygen in the sample. The sample is aerated, and a computer is used to sample the signal at regular intervals to produce a series of time-separated values corresponding to the sampled signals, the values representing the dissolved oxygen in the sample at the timed intervals. Repeated samples can be taken, so that the O.U.R. can be monitored on a continuing basis. The O.U.R. information can be used to control the rate of aeration in a tank, or to control the rate of recycling of activated sludge from the downstream to the upstream end of the tank.