Abstract: A stack layer structure is formed wherein solderable metal layers are provided at least at two ends thereof, and at least a metal layer for preventing the diffusion of solder is inserted between the two metal layers. In an interboard connection terminal and a method of manufacturing the same, a pair of solder bumps are fixed to be in contact with the two surfaces of the resultant stack layer structure.

Abstract: An electronic component module is mounted on a motherboard. An elongated slot is formed in the module. A pair of ejector handles are mounted with the slot. A first leg portion of each handle is mounted on one side of the slot and a second leg portion is mounted on an opposite side of the slot. Each handle has a first end including an aperture formed in each leg and a second end including a flange. A pin connection extends through the apertures and the slot for pivotally and slidably connecting the handle to the module. Each handle is slidably movable from a first end of the slot to a second end of the slot adjacent a supporting chassis. The handles can then be pivoted outwardly away from the module until contacting the chassis, and then urged downwardly into engagement with the chassis thus unseating and lifting the module from nested engagement with the motherboard.

Abstract: A dual cavity semiconductor package containing a high voltage (greater than 1500 volts) isolation amplifier includes a ceramic substrate with tungsten metalization thereon defining die bonding and wire bonding sites and interconnections in the two cavities for input and output circuitry of the isolation amplifier, respectively. The metalization also defines a pair of precisely matched planar fringe capacitors forming a high voltage small signal isolation barrier located between the two cavities. A layer of ceramic having apertures therein defining the two cavities is laminated over the substrate. The assembly is cofired at about 2,000.degree. Centrigrade, causing ceramic to fill the gaps between the conductors of the fringe capacitors, providing very high voltage isolation therebetween. Separate tungsten sealing rings are provided around the peripheries of the cavities on the top surface of the second layer.

Abstract: A electronic multilayer device is formed within a photocured insulative layer using a transparent substrate thereby forming a surface contamination free device without shorts between the layers of the device.

Abstract: A heat-resistant plastic-packaged semiconductor device comprises an IC chip having contacts on its first surface, an island on which the IC chip is mounted with its second surface facing a first surface of the island, a low-adhesion layer which is formed on a second surface of the island, external leads, bonding wires for connection of the contacts on the IC chip and inner ends of the external leads, a package of mold resin for encapsulating the IC chip, the low-adhesion layer, the bonding wires and inner parts of the external leads, the mold resin being provided with a vent hole which extends to the vicinity of the low-adhesion layer. The low-adhesion layer has a low or no adhesive power to the mold resin.

Abstract: A printed board capable of permitting the passage of at least two wiring patterns between two adjacent mounting lands on the surface of the printed board even if a clearance between the adjacent mounting lands is limited. Mounted on the printed board is an electrical component having a plurality of leads extending in a parallel relation with each other with limited clearances formed between adjacent leads. The printed board has a plurality of mounting lands to which the respective leads of the electrical component are secured as by soldering, there being a limited clearance defined between adjacent ones of the lands such that only one wiring pattern printed on the printed board can run through the clearance in the direction parallel to that in which the leads extend.

Abstract: A system and method for the construction of one-dimensional maps from fragmentation data is disclosed. Particularly useful for construction of restriction maps of DNA, the system and method completely permutes sites, single digest fragments, and any available multiple digest fragments, and displays maps in rank-order according to a quality factor. Display of constructed maps includes information about relative ordering of all fragments, sites, and particularly about closely-spaced sites and fragments.

Abstract: An optoelectronics device wherein a light-receiving element which defines a monitor light receiver and a semiconductor laser which generates a laser beam are hermetically sealed in the same package, and wherein the light-receiving surface of the element for measuring the output power of the beam of light emitted from the semiconductor laser is disposed so as to be inclined with respect to the light-emitting surface of the semiconductor laser. The wire bonding surface of the light-receiving element pellet-bonded to a stem and the wire bonding surface of the lead electrically connected to the light-receiving element through a wire are arranged so as to be parallel with each other. Thus, it is possible to support both the bonding surfaces horizontally at the same time. As a result, a bonding tool can be brought into perpendicular contact with each of the bonding surfaces, and this enables appropriate wire bonding to be effected.

Abstract: An electronic packaging structure, and a method of making this structure, are disclosed. The electronic packaging structure comprises a full panel, circuitized flexible film semiconductor chip carrier mounted on a circuitized substrate such as a printed circuit board. A plurality of semiconductor chips are mounted on the carrier in a selected pattern, and the carrier, with the chips, is mounted on a matching pattern of bonding sites on the circuitized substrate. Preferably, the circuitized flexible film semiconductor chip carrier is manufactured on a support structure used to facilitate handling of the circuitized flexible film and to facilitate heat transfer from the semiconductor chips mounted on a carrier to a heat sink which is part of the circuitized substrate. Also, the semiconductor chip mounted on the flexible film chip carrier may be tested, and burned in, while on the support structure before the chip carrier, with the chips, is mounted on the circuitized substrate.

Abstract: A semiconductor device having improved heat-dissipating characteristics employs a thin insulator film made of diamond, which has excellent thermal conductivity, as an insulator film which is formed on a chip immediately below a heat-dissipating bump electrode. Since the thin diamond film has excellent insulating properties and high thermal conductivity, it is possible to improve heat-dissipating characteristics of even a high-power semiconductor device such as a multichip module. In the case of, particularly, a multichip module, the insulation between a mother chip and a child chip can also be ensured by the presence of the thin diamond film.

Abstract: An electrical assembly having an integrated circuit package which has a plurality of electrical conductors fixed thereto. The electrical conductors form mechanical and electrical connections. Each of the electrical conductors has a root at one end and a tip at the other end. The root of each conductor is attached to the integrated circuit package to form a fixed electrical and mechanical connection. The tip of each conductor is adapted to be connected to a surface at a predetermined location. Each of the electrical conductors has at least two bends between the root and the tip for providing strain relief when the tip is connected to a surface.

Abstract: A mechanical interlock arrangement is disclosed for preventing misinstallation of a plurality of associated PC boards in the mainframe chassis of an electrical or electronic apparatus. Each PC board is mounted to a subpanel which has a mounting flange with a uniquely located key tab. This keying tab is accommodated within a selectively located slot on a member positioned traverse the front face of the mainframe chassis. The keying tab may be located along the top or bottom of the mounting flange and is made of substantially rigid material to prevent such protective keying function from being easily defeated.

Abstract: A high density of electronic chips 18 includes decals 26,40 which overlay a chip and an adjacent chip. Each decal includes conductor routing 64,67,69,80 to electrically connect the chip circuits. The decals may include capacitors 53,58,60 and terminating resistors 81. The chips are directly connected to the frame 112 or heat sink 116 which may be double sided.

Abstract: A multilayer printed circuit board is provided comprising a plurality of printed circuit boards laminated together, each board being separated from an adjacent board by a layer of a dielectric of porous, expanded polytetrafluoroethylene (PTFE). The dielectric layer may have an adhesive on its surface(s) affixed as a layer or in a pattern of dots. Alternatively, an adhesive may be impregnated within the pores of the porous dielectric. In a preferred embodiment, the dielectric has additional openings or through holes in it, in additon to the pores of the porous dielectric.

Abstract: A substrate connector guide for installing and electrically connecting an electrical substrate to a carrier substrate. The substrate connector guide includes a plurality of guide rails mounted on the perimeter edge of the electrical substrate and at least a first electrical connector mounted transversely between the guide rails. First and second substrate guides are mounted to the carrier substrate in a spaced and parallel relationship to the other. Each substrate guide includes a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. At least a second electrical connector is mounted and electrically connected to the carrier substrate between the first and second substrate guides.

Abstract: A substrate connector guide for installing and electrically connecting an electrical substrate to a carrier substrate. The substrate connector guide includes a plurality of guide rails mounted on the perimeter edge of the electronical substrate and at least a first electrical connector mounted transversely between the guide rails. First and second substrate guides are mounted to the carrier substate in a spaced and parallel relationship to the other. Each substrate guide includes a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. At least a second electrical connector is mounted and electrically connected to the carrier substrate between the first and second substrate guides.

Abstract: An electrical component for mounting on a circuit substrate densely populated with conducting paths, includes interconnecting conductor paths included within the electrical component and unrelated to the electrical device supported by the component support structure in order to provide an interconnection between two conducting paths of the circuit substrate.

Abstract: A large scale integrated circuit package is described wherein insulating layers of an organic material are provided between wiring layers to reduce the characteristic impedance of signal wiring. To avoid deformation of the organic insulating layers and subsequent damage to wiring layers, leads for connecting the circuits of an integrated circuit chip to electrode pads are mechanically connected to the electrode pads on an upper layer of organic insulating material by a gold-tin eutectic alloy.

Abstract: An electrical junction system for automotive internal wiring has a wiring board provided with branching conductors formed by a multiplicity of bus bars on an insulation plate, the branching conductors being adapted to be connected to electric wires in a wiring harness to form branching electric circuits. The electrical junction system has a printed circuit board detachably mounted on the wiring board, the printed circuit board generally or inclusively carrying a plurality of circuits incorporating a multiplicity of function parts which are used semi-permanentally such as relays and associated control elements.

Abstract: A speaker having a slotted flange is attached by a robot to printed circuit board mounting posts. The posts are slotted and dimensioned so the post slots are slid into engagement with the flange slots in interlocking arrangement. The posts and flange are dimensioned so that a robot hand can slide the flange between the posts in interference fit such that the relatively rigid posts are torqued apart flexing the board. When the flange and post slots engage, the board flex forces snap the posts and flange in locked engagement.