Abstract: One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.

Abstract: The present invention provides a reduction checksum generator for calculating a checksum value for a block of data. In one embodiment, the reduction checksum generator includes a reduction unit having a plurality of reduction stages and configured to pipeline a plurality of segments of the block of data through the plurality of reductions stages to reduce the plurality of segments to at least two segments. The reduction checksum generator also includes a checksum unit configured to generate a one's complement sum of the at least two segments and invert the one's complement sum to produce the checksum value. In addition, a method of calculating checksum value using reduction for a block of data and a parallel reduction checksum generator are also disclosed.

Abstract: Provided are a method, system, and article of manufacture for providing data integrity for data streams. Input data streams are received. A parity data stream is generated by computing parity data from the input data streams, wherein the parity data stream comprises data blocks. Data integrity fields are computed for the data blocks, wherein a data integrity field is used to ensure the integrity of a data block for which the data integrity field is computed. The computed data integrity fields are added to the data blocks to generate an output stream.

Abstract: An error correction coding device includes a time divider for dividing field data of L packets into N data packets and (L-N) parity packets, a first RS (Reed-Solomon) encoder adding parities of a predetermined number of bytes to the data packets, respectively, a storage unit for storing the data packets, and a second RS encoder generating parity packets corresponding to the stored data packets. An error correction decoding device includes a first RS decoder correcting errors in a horizontal direction of the field data using parities of the predetermined number of bytes included in the L packets, a storage unit storing the error-corrected data packets, and a second RS decoder correcting errors in a vertical direction of the field data using the parity packets. Thus, the error correction can be strongly performed using parities existing in the horizontal and vertical directions with respect to the field data.

Abstract: A method for generating parity codes of a data sector having data information and main data. The main data is scrambled to generating outer-code parity. The main data is scrambled to generating inner-code parity. The outer-code parity generating is superior to the inner-code parity generating. The outer-code parity is generated by vertically scrambling the corresponding vertical data block.

Abstract: A method and system for ensuring data integrity in a data processing system may comprise monitoring when data for a specified device is available for error correction code generation, and receiving a first indication of the specified device, a second indication of the data, and a third indication of a size of the data during the monitoring. A new error correction code may be generated in hardware for the data based on the indicated size of the data and an indication may be provided to signal when generation of the new error correction code for a specified number of accesses for at least a portion of the data is complete. Detected errors may be corrected in software based on the newly generated error correction code. The first indication may be a device selection signal and the error correction code generation may be enabled or disabled via an enable signal.

Abstract: A storage device comprising a storage medium having a plurality of sectors and a superset format. Each sector includes a header, a data section and a trailer, the data section sized to contain a number of bytes per sector equal to or greater than a maximum of subset formats to be supported. Meta data in a non-user portion of the storage medium includes a flag for indicating a subset format such that each sector is formatted to store less than the number of bytes.

Abstract: A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.

Abstract: A method and apparatus for generating an error correction code used in communicating over a channel, includes generating a set of candidate circulant blocks corresponding to a parity check matrix and a Hamming code wherein the Hamming code is initially unable to detect a predetermined error pattern without ambiguity due to one or more redundancies and eliminating columns of the parity check matrix and related redundancies in the detection of a predetermined error pattern as used by the resulting Hamming code.

Abstract: A method, an apparatus, and a computer program are provided for generating an error detection state and correction of code patterns. Generally, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment is difficult. A circuit, however, can be employed that periodically detects the functionality of the dI/dt circuit to indicate success or failure. When errors are detected, the circuit allows for erroneous codes to be replaced with accurate ones. Using this circuit, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment can be more easily achieved.

Abstract: A base sequence S(j) is not directly calculated but is indirectly calculated by the use of a numerical sequence M(n)=[v×n] mod p. A value of M(n) can be calculated by a recurrence formula without requiring modulo calculation. The value obtained is stored in a memory. M(n) satisfies S(j)=M(S(j?1)). By determining an initial value of S(j) and interleaving the value of M(n) stored in the memory, the base sequence S(j) can be calculated without modulo calculation.

Abstract: A device and method of applying a parity to encrypt data for protection is disclosed. A parity generator generates a parity bit in accordance with a data to be outputted. A first parity location generator generates an inserting position N for the parity bit in accordance with a predetermined algorithm. A parity-inserting unit inserts the parity bit in a position between (N?1)th- and Nth-bit of the data in accordance with the inserting position N, thereby generating an encrypted data.

Abstract: A system for detecting errors in received input data includes a first error detection circuit. The first error detection circuit is configured to receive the input data. The input data includes at least one of data and data with errors. The first error detection circuit is configured to generate a first error detection sequence in a first order. The system includes a second error detection circuit. The second error detection circuit is configured to receive the first error detection sequence and an error sequence. The error sequence is received in a second order that is different from the first order when there is data with errors. The second error detection circuit is configured to generate a second error detection sequence that indicates whether the error sequence is generated correctly.

Abstract: An error handling apparatus and method, and a computer-readable medium storing a computer program for executing the error handling method are provided. According to the method, in a case where a number of errors in object IP packets that are consecutively detected, each within a first predetermined time since a previous error detection, exceeds a maximum allowable number of errors, communication with a sending node of the erroneous IP packets during a second predetermined time is discontinued. Also, errors can be handled with reference to a cache unit including more than one entry identified by an address of a corresponding erroneous IP packet. Therefore, a network load of a receiving node can be reduced by not transmitting an internet control message protocol (ICMP) packet to a sending node where indiscriminate IP packet manipulations or denial of service (DoS) attacks are suspected during the second predetermined time.

Abstract: A stable system is provided wherein the influence of disturbance or the like can be reduced. First error correcting code units and second error correcting code units are used, and thereby a wider range of random errors and burst errors are made correctable to avoid retry operation. Thus, stable data reproduction is carried out without degrading transfer rate. Further, the constitution of error correcting blocks is set so that when a head is moved to some track during seek operation, a sector having the second error correcting code recorded therein is the first sector to be read.

Abstract: In a packet-based data transmission including incremental redundancy (IR) protocols, the memory consumption of the IR protocol is reduced by compressing and storing failed data units in their punctured format. The failed data units are compressed using low complexity compression/decompression algorithms. The compression algorithm includes two parts: calculating and storing a scale factor for each transmission burst that estimates the soft values in the burst, and storing each soft values' sign in local memory instead of the complete soft value. If the currently received data unit is a retransmission, its compressed versions in the punctured format stored in the IR memory are decompressed, de-punctured and combined with the currently received data unit. The combined data unit is then decoded. The decompression restores an estimated soft-value by multiplying the sign value stored in the IR memory with its corresponding scale factor obtained from a mapping table.

Abstract: A method and mechanism for managing dynamically allocated memory. Portions of memory which are available for allocation have additional information stored in association with each portion which indicates whether the portion has been previously identified as being prematurely freed. In addition, a checksum is stored with each portion of memory. In response to a request for deallocation of a portion of memory, the portion of memory is not deallocated if it is identified as having been prematurely freed. Otherwise, the a checksum is calculated for the portion and it is freed. In response to an allocation request, a candidate portion of memory is identified for allocation and a checksum is calculated for the candidate portion. If the calculated checksum does not match a checksum previously stored for the candidate portion, the portion is identified as having been prematurely freed and is not returned for allocation.

Abstract: An approach is provided for efficiently decoding low density parity check (LDPC) codes. An LDPC decoder includes a memory for storing a mapped matrix that satisfies a plurality of parallel decodable conditions for permitting a lumped memory structure. Additionally, the decoder includes a parallel processors accessing edge values from the stored mapped matrix decode the LDPC codes. The above approach has particular applicability to satellite broadcast systems.

Abstract: A communication system includes an encoder that receives user data and includes running digital sum encoding and turbo encoding. The running digital sum encoding is preserved in an encoder output to a channel. A decoder receives a channel output and comprises running digital sum decoding and turbo decoding to reproduce the user data in a decoder output.