Abstract: There is provided a method of encoding a data word. The method includes encoding a first occurrence of the data word to produce a first code word, and encoding a subsequent occurrence of the data word to produce a second code word. The second code word and the first code word are different from one another.

Abstract: In a method for a variable-length communications system including encoding a message and decoding a data bit stream, the message includes a plurality of message blocks. A message block of the message is encoded by generating a parity check bit stream, flipping the parity check bit stream, and appending the flipped parity check bit stream to the end of the message block. When a data bit stream is received, a guessed message block and a guessed flipped parity check bit stream are extracted based on a guessed message block length. A parity check bit stream is generated for the guessed message block and then flipped. If the flipped parity check bit stream is the same as the guessed flipped parity check bit stream, the message block has been identified. Otherwise, the guessed message block length is increased by 1 and the above step is repeated.

Abstract: The disclosed embodiments relate to a system and method of refreshing metrics. The method may comprise obtaining a plurality of data elements that comprise information about a process and computing a plurality of metrics from a plurality of mappings, each of the plurality of mappings relating to an operation on at least one of the plurality of data elements. Each of the plurality of metrics may have a refresh rate. Additionally, the method may comprise analyzing the refresh rate of the plurality of metrics to identify at least one shared refresh interval between groups of the plurality of metrics, identifying at least one common mapping between the plurality of metrics, and periodically refreshing the plurality of metrics, accounting for the at least one shared refresh interval and the at least one common mapping between the plurality of metrics.

Abstract: A turbo encoded H-ARQ system and an error detection method are disclosed, and more particularly, a turbo encoded H-ARQ system and an error detection method that lower an undetected error probability and frame error rates by increasing the degree of an equivalent CRC generator polynomial by using a modified trellis termination. It has been made possible to obtain an equivalent CRC generator polynomial having higher degree than the related art CRC generator polynomial by employing a modified trellis termination. This achieved a lower undetected error probability than the related art undetected error probability by using an equivalent CRC generator polynomial having higher degree. This also achieved lower frame error rates, when the same number of overhead bits are used, due to the lower undetected error probability.

Abstract: Techniques for detecting and correcting burst errors in data bytes formed in a two-level block code structure. A second level decoder uses block level check bytes to detect columns in a two-level block code structure that contain error bytes. The second level decoder generates erasure pointers that identify columns in the two-level block structure effected by burst errors. A first level decoder then uses codeword check bytes to correct all of the bytes in the columns identified by the erasure pointers. The first level decoder is freed to use all of the codeword check bytes only for error byte value calculations. The first level decoder does not need to use any of the codeword check bytes for error location calculations, because the erasure pointers generated by the second level decoder provide all of the necessary error locations. This techniques doubles the error correction capability of the first level decoder.

Abstract: The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable.

Abstract: An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.

Abstract: A received RF signal can include data information intended for transmission over a wireless communication link. The data information of the signal can be processed at a node to produce overhead bits supporting a serial transmission of the data information over a communication medium to another node. For example, the data information of the received signal and overhead bits can be combined or framed according to a serial transport protocol for transmission over the communication medium. This technique of mapping or framing the data information into a serial transport protocol is used to more efficiently transmit the data over the communication medium to a target receiver, where the original RF signal can be reconstructed.

Abstract: Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.

Abstract: A method, system, and article of manufacture for recovering from a track format error detected by a host computer associated with a storage controller associated with a storage disk array. The recovery method begins with saving a copy of the track format information associated with the data track that triggered the track format error in a predetermined location. Next, the track format information associated with the data track that caused the error is invalidated and the subject data is restaged. Subsequently, the restaged data is compared to the saved copy of the track format information to determine if the track format error exists with respect to the restaged data. If the track format error is detected with respect to the restaged data, the method further consists of reconstructing the data, preferably by performing a reconstruct read recovery.

Abstract: A recording-medium cartridge including a recording-medium and a cartridge memory. In this recording-medium cartridge, the cartridge memory holds a unique cryptographic key in the condition that the rewrite of the cryptographic key is forbidden, and is detachably attached to the recording-medium cartridge. The recording-medium holds a CRC-code, which is generated based on the cryptographic key and data to be recorded on the recording-medium, and data in the condition that the CRC-code is correlated with the data.

Abstract: A decoding method for coded data representing original data. Corrupted data is detected and replaced with buffered data. The buffered data is stored in the buffer a time interval corresponding to an estimated periodicity or an integer multiple thereof before the corrupted data was received. The estimated periodicity is determined by estimating the periodicity of the original data represented by the corrupted data.

Abstract: A method of decoding soft input information related to a transmitted word of a linear block code (n, k) and providing hard or soft output information is disclosed. The method comprises the steps of forming a reliability vector from the input information, identifying (n?k) linearly independent least reliable symbols and k most reliable symbols, converting a parity check matrix of the linear block code to a pseudo-systematic form with respect to the least reliable symbols, calculating extrinsic information and composite information for the most reliable symbols using the soft input information and the pseudo-systematic parity check matrix, and calculating extrinsic information for the least reliable systems using composite information for the most reliable symbols.

Abstract: Data is stored using multiple selected network nodes in a network based on encoding of the data into multiple distinct encoded data units according to a prescribed encoding operation. The secure encoding operation generates a first prescribed number of encoded data units, whereas merely a second prescribed number of the encoded data units are necessary for recovery of the original data, the second prescribed number being less than the first prescribed number. The encoded data units are distributed among selected network nodes in a network, where any one network node receives less than the second prescribed number to ensure security. A requesting node recovers the original data by requesting the second prescribed number of encoded data units from among the network nodes having stored the respective encoded data units.

Abstract: A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit nibble is used to detect up to 8-bit errors and correct data errors of 4 bits or less. Rather than generating address parity, which is poor at detecting even numbers of errors, a cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to just 4 address check bits using the CRC code. The 4 address check bits are merged (XOR'ed) with two 4-bit nibbles of the data SbEC/DbED code to generate a merged ECC codeword that is stored in memory. An address error causes a 2-nibble mis-match due to the redundant merging of the 4 address check bits with 2 nibbles of data correction code. The CRC code is ideal for detecting even numbers of errors common with multiplexed-address DRAMs.

Abstract: A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller includes a read data module to read the user data and parity information, determine whether there is error in the user data based on the parity information, read the error correction information if there is error as determined based on the parity information.

Abstract: A method of estimating the reliability of decoded message bits in a digital communications system is proposed. Message and tail bits are coded and transmitted across a communications channel. The coded message and tail bits are then decoded and it is determined that the decoded message bits have no error when the decoded tail bits have at least one error.

Abstract: The present invention is related to an error handling in transmission of information units in radio links and in particular it is related to an error handling using automatic repeat request (ARQ) and transmission of information units in mobile communication. To reduce the access delay of packet data services, the present invention uses different code ratings according to type II hybrid ARQ for different erroneous information units selected from a formatted block of information units before retransmission. Therefore erroneous information units of a block of information units, that have been transmitted, are selected and the set of selected erroneous information units is divided into a set of n subsets encoded with n code ratings. Advantageously, the retransmission of portions of the formatted block with different code ratings enhances the reliability of the retransmission.

Abstract: When an error is detected in a received header, in estimating reference information while assuming an error in a packet receiving interval, a header is decompressed using at least one value of another candidate sequence numbers used in correcting an erroneous sequence number, corresponding to a time that elapses between previously receiving a packet correctly and receiving a current packet and to the packet receiving internal. It is thereby possible to increase a possibility of estimating the reference information correctly and suppress the number of discarded packets at a receiving side, while suppressing increases in introduced processing amount in data transmission with header compression.

Abstract: The waveform equalizing device includes: an FIR filter for generating an equalized signal pattern y(i, n) on the basis of equalization of a waveform of the reproduced signal pattern u(i, n); a Viterbi decoding circuit for detecting a path metric difference s(n) between a correct path determined as a survivor path and an error path which fails to survive the correct path in Viterbi decoding based on the equalized signal pattern y(i, n); a target register for setting a target value ds for the path metric difference s(n); and a tap coefficients update circuit for adapting the equalization according to an error of the detected path metric difference from the target value. The tap coefficients update circuit adapts equalization properties so that the mean square error is minimized, thereby achieving a satisfactory result in lowering the error rate.