Abstract: In one embodiment, a method may determine a number of data transitions occurring in a forbidden zone at each of a first and second slice levels and adjust a slice level offset for an amplifier based on the number of data transitions at the first and second slice levels. Furthermore, a phase window of the forbidden zone may be adjusted to attain a desired bit error rate for a receiver.

Abstract: When it is detected that a CRC check is acceptable in Blind Transport Format Detection (BTFD) processing, the BTFD processing is halted from this moment onward, the number of bits of voice code of each class is decided based upon the bit rate of each class in a bit-rate combination that prevails when the CRC check is acceptable, the voice code of each class is demultiplexed from receive data based upon the number of bits and the demultiplexed voice code is input to a voice codec.

Abstract: If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations which can be performed is restricted. To solve the above problems, the present invention can record data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention.

Abstract: A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

Abstract: A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Abstract: A packet detection technique is disclosed in which an average correlation signal is generated representative of the match between a repetitive sequence of symbols; an average power signal is generated representative of the average power in the sequence of symbols; a scaled magnitude of the average correlation signal scaled by a first predetermined scale factor is produced; and one of the average power signal and scaled magnitude of the average correlation signal are multiplied by the second scale factor and compared to determine whether there is a match between a repetitive sequence of symbols.

Abstract: A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.

Abstract: A method of and system for generating reliability information for a noisy signal received through a noise-introducing channel. In one embodiment, symbol-transition probabilities are determined for the noise-introducing channel. Occurrences of metasymbols in the noisy signal are counted, each metasymbol providing a context for a symbol of the metasymbol. For each metasymbol occurring in the noisy signal, reliability information for each possible value of the symbol of the metasymbol is determined, the reliability information representing a probability that the value in the original signal corresponding to the symbol of the metasymbol assumed each of the possible values. In another embodiment, error correction coding may be performed by adding redundant data to an original signal prior to transmission by the noise-introducing channel and performing error correction decoding after transmission.

Abstract: The present invention provides a data processing apparatus and method for handling corrupted data values. The method comprises the steps of: a) accessing a data value in a memory within a data processing apparatus; b) initiating processing of the data value within the data processing apparatus; c) whilst at least one of the steps a) and b) are being performed, determining whether the data value accessed is corrupted; and d) when it is determined that the data value is corrupted, disabling an interface used to propagate data values between the data processing apparatus and a device coupled to the data processing apparatus to prevent propagation of a corrupted data value to the device. When a data value is accessed, the data processing apparatus can begin processing of that data value and, hence, the performance of the data processing apparatus is not reduced.

Abstract: In a data recording method and a data recording apparatus relating to the present invention, ECC blocks using 36 product codes are recorded on 12 tracks through scanning operations performed three times. First of all, first sync-blocks each constituted by adding a C1 parity to the data string of video data constituting an internal encoding calculation data stream are sequentially recorded. When the first sync-blocks are completely recorded, second sync-blocks each constituted by adding the C1 parity to the data string of C2 parity constituting the internal encoding calculation data stream are sequentially recorded. By recording the C2 parity at one time in a later stage, the system delay can be minimized.

Abstract: A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0xFF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and the error correction code converting circuit converts the set of correct error correction codes into 0xFF error correction codes, and values stored in the data area and error correction code area of the flash memory are converted into 0xFF to prevent wrong error correction code from occurring during data reading operation when the error correction codes are not completely 0xFF.

Abstract: The invention relates to a method for enabling most reliable packet orientated data transfer to take place by using an ARQ-method, especially a hybrid-ARQ-method, preferably for use in a mobile radio system. The invention also relates to a bit rate adaptation model which is used for signaling between the transmitter and the receiver.

Abstract: FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.

Abstract: (3n+1)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a first memory 102, (3n+2)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a second memory 103, and (3n+3)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a third memory 104. Information bit, first parity bit, and second parity bit that have been read out by 3 bits are held in an information bit queue 108, a first parity bit queue 109, and a second parity bit queue 110, respectively, to control data supply to the rate dematching circuits 111 and 112 by these queues 108, 109 and 110.

Abstract: Techniques are provided for performing early decoding of a message on a control channel in a wireless (e.g., GSM) communication system. In a GSM system, a message for a paging channel is transmitted in four bursts. For early decoding in GSM, a terminal initially receives the first two bursts for the message. The two bursts are processed and decoded to recover the message, which is then checked to determine whether it has been decoded correctly or in error. The decoding process can terminate and the terminal may go to sleep early if the recovered message is good. Otherwise, the third burst is received, and all three bursts are processed and decoded to recover the message. Again, the decoding process can terminate if the recovered message is good. Otherwise, the fourth burst is received, and all four bursts are processed and decoded to recover the message.

Abstract: A method and an apparatus for transmitting error-tolerant data is disclosed employing the ARQ technique, wherein the retransmission of erroneous data is performed up to the point where the remaining amount of errors is acceptable (for instance because the erorrs will not be perceived by the recipient of the information, which can be a person or a higher level protocol with additional error correction capabilities). The number of data blocks (RLC) detected as erroneous is employed to define a reliability measure (RM) and a request for retransmission of the erroneous data blocks is performed until a desired reliability threshold (RT) is reached. An additional threshold with a higher value than the first one can be employed to request for optional retransmission when the reliability measure (RM) is between the first and the second threshold. The retransmission will be performed only if further conditions such as channel availability are met.

Abstract: A method and apparatus for decoding turbo encoded data. A first turbo decoding iteration is performed to produce a most likely sequence of symbols, each symbol having an amplitude value and a positive or negative sign. The sequence of symbols is error checked, and if an error is detected, the apparatus forms a next most likely sequence by reversing the positive or negative sign of the symbol having the smallest amplitude. If an error is again detected, additional sign reversals are performed on symbols with larger amplitudes, and on multiple symbols. Each modification is error checked. If none of the modifications produce an error-free sequence, and a maximum number of modifications are performed, the apparatus performs another turbo decoding iteration to produce another sequence of symbols. The process is then repeated until an error-free sequence is produced or a maximum number of iterations are performed.

Abstract: Methods and structures are provided to improve the transfer functions of analog-to-digital converter systems. They address the converter error function that corresponds to a converter's transfer function. In particular, they provide a corrector with a corrector transfer function that defines a corrector error function which substantially mirrors at least a portion of the converter error function. The corrector processes the converter's output digital signals to realize corrector digital signals which are then combined with the original output digital signals to obtain a system with a system error function that is significantly reduced from the original converter error function.

Abstract: An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number of bit errors in a bit stream, long strings of ones and zeros are easily suppressed by detecting a prohibited length of ones or zeros, and flipping a bit in the string of ones or zeros. This method and system removes the violation of the ones or zeros bit string requirement by flipping a bit in the string, while the receiving side utilizes the error correction capability of the ECC/FEC to correct the inverted bit.

Abstract: In a system and an associated method, for data transmission in a computed tomography device, having a data acquisition unit in which measurement data are acquired, converted into a bit stream, and communicated to a transmitter apparatus on a rotating part of the computed tomography device, wherein the transmitter transmits the bit stream to a stationary part of the computed tomography device, and having a receiver apparatus on the stationary part that receives the bit stream from the transmitter apparatus and communicates it to an image reconstruction unit that further processes the bit stream communicated by the receiver apparatus for the reconstruction of the image, the transmitter apparatus and the receiver apparatus each have an error recognition module that monitors the bit stream for errors and signals recognized errors to an error processor that determines the number and rate and/or duration of the recognized errors and stores these in a log data file for an evaluation.