Abstract: A method and system of maintaining continuity of computer control and information exchange between moving vehicles such as aircraft and a computer, with a different computer being operative as a given moving vehicle moves from a first defined sector to a second defined sector, the data link between each computer and the moving vehicles located in its sector being provided by radio transmission. Each sector has a different given transmission frequency. A transition area is defined at the interface between the first and second defined sectors wherein the moving vehicle is under joint control of the computers of the successive sectors.

Abstract: Procedure and system for driving a vehicle required to travel repeatedly over the same path, in which procedure at least some elements of the vehicle are operated in accordance with prerecorded information.According to the invention, the information relates to the operations to be performed on or by such elements in relation to the position of the vehicle on its path; and the elements are operated on the basis of such information in the light of the vehicle's instantaneous position with a correction for instantaneous vehicle speed and the response time of the elements.

Abstract: The specification discloses a check digit verification apparatus having the following novel concepts1. the use of a read-only store (16) to hold tables of remainder values whereby to obviate the need for multiplication computing ability;2. the use of remainder values appropriate to the respective digits of an identity number to be verified, and summation of those remainder values to provide an overall remainder value for the identity number;3. the use of a remainder value accumulating store (23) having a number of stages equal to the modulus of the system, so that the contents of the store is an accumulated remainder value, thus obviating the need for a `division` computing ability; and4.

Abstract: A method for operating an aircraft at the minimum total flying cost per unit of distance. The fuel cost per unit of distance and the flying time cost per unit of time are calculated at a first fuel flow setting and are added together to obtain a total flying time cost per unit distance. After a predetermined time interval, a second fuel flow setting is entered into the aircraft and a second total flying time cost per unit distance is calculated and compared to the first. The fuel flow setting is again adjusted in the direction of the minimum total flying time cost per unit of distance. This procedure is repeated until the minimum is found, and can be repeated thereafter at specific intervals to assure that the minimum is maintained.

Abstract: A method and system of preventing collisions between aircraft comprising defining an imaginary airspace around the center of each aircraft, the airspace having a given radius (R) and height (H), and moving with and at the same velocity as the aircraft. An imaginary airspace having zero velocity is defined around objects of terrain and the parameters of each defined airspace are updated as the corresponding aircraft travels. The parameters of each aircraft defined airspace is compared one at a time with the parameters of all other defined airspaces within a discrete altitute band under predetermined criteria to determine whether there is an existing or future travel course conflict, and an indication is produced in the event such a conflict is determined.

Abstract: A computer apparatus includes means for comparing the address stored in an address register with a preset address. When the stored address matches the preset address the comparison means issues an alarm signal which may be used to effect an immediate halt in the execution of a routine, trigger suitable annunciators or, selectively, to enable the injection into the routine of an overriding preset instruction.

Abstract: The invention provides a compact test sequence for testing integrated memories. First, all storage positions are filled with the bit "0". Subsequently, in a given order of the addresses, the "0" bit written for each address is read; immmediately thereafter a "1" bit is written in those bit positions. The positions are again tested by reading the "1" bits. When the last address of the predetermined order is reached, the "1" is read in the same order for each address. Subsequently a "0" is written, which is finally tested by reading again. When the last address is reached, all addresses are read in the reverse order, and a "1" is written, which is tested again. When the first address is reached, all addresses are read, filled with a "0" and tested. This process may be repeated as many times as there are bits in the address. The significance of the address bits are modified to form the predetermined order, for example, by cyclic rotation.

Abstract: There is provided a coordinator for creating a desired background cycle time and controlled logic conditions on selected output circuits during the background cycle which cycle and logic conditions are used in governing the signalization of a traffic intersection. This coordinator includes a pulse counter for counting between 0 and 99 upon receipt of counting pulses and having output means for creating a distinct signal upon counting to each digit in the range of 0 to 99. There is further provided means for controlling the frequency of the counting pulses to a frequency equal to one hundred divided by the time of a desired background cycle in seconds and decoding means for creating the selected logic conditions in output circuits when the counter counts to a selected number in the range of 0 to 99.

Abstract: An improvement in a digital coordinator of the type used for creating a background cycle defined by a series of control pulses repeatedly cycled between a first number, N.sub.1, and a second number, N.sub.2, with the time space between the N.sub.1 control pulse and the N.sub.2 control pulse being a background cycle length. This type of coordinator comprises a primary pulse counter means incremented by input counting pulses for creating one in a series of control pulses in response to a selected number of input counting pulses, wherein the input counting pulses have a selected frequency for determining the cycle speed of progression of the control pulses in successive count positions between the N.sub.1 control pulse and the N.sub.2 control pulse of a given background cycle, and shifting means for shifting the N.sub.1 control pulse with respect to time to correspond in time with a synchronization offset signal.

Abstract: This invention relates to a process for preventing undesired contact with land or water by low-flying aircraft which are assigned a minimum altitude and which are provided with instruments for measuring altitude, airspeed, angle of path, and transverse acceleration,Comprising measuring the rate of descent (H),transverse acceleration (b.sub.Q), when gravitational acceleration is eliminated,And altitude (H) to thereby ascertain whether the aircraft is above a given limiting altitude (H.sub.limit) determined from its ability for transverse acceleration and its flight data,And correcting the aircraft by the maximum feasible transverse acceleration (b.sub.Q max) when for a given measured value of altitude (H), the altitude is below the limiting altitude (H.sub.limit).

Abstract: An address converter for converting first addresses into second addresses which are fed to a memory of the data processing device, where the first addresses contain first and second address words and the second addresses contain third and fourth address words, the address words representing binary numbers, employs a comparator which is supplied with the first address word and a predetermined binary number and which is responsive thereto to emit a binary signal which assumes a first or a second binary value when the first address word is smaller than, or is not smaller than, respectively, the binary number, a transfer switch which assumes a first condition and a second condition when the binary signal assumes the first and second binary values, respectively, and which in the first and second positions, respectively, switches through the first address word or the binary number as a third address word, respectively, and an allocator which is supplied with the first and the second address words and which emits th

Abstract: A virtually addressed multilevel mass storage system (MSS) has error recovery and definition procedures and apparatus for controlling and enabling recovery from error conditions in an upper storage level. A plurality of possible error conditions in an upper level gives rise to errors in destaging data signals to a lower level, plus possible overwriting good data with data in error. A first such error condition is a data error detected during a destage. A second such error condition is repeated upper-level equipment (not data) errors. Both errors make data integrity of the lower-level suspect. Corrective action for a plurality of errors includes coordination with a host computer, reconfiguration, destaging data in error after precautionary steps, and preserving data in error at the failing upper level unit which is used in virtual mode except for the portion yielding the error condition.

Abstract: Apparatus and method are described wherein the average access time utilized for recovering stored data in a random access storage system is reduced. An access cycle is begun with the predetermined typical data bit delivery time known and with the knowledge of the worst case data bit delivery time. An output buffer is connected to a random access storage for receiving the data bits of an output message from the storage. The output buffer is gated to receive the data from the random access storage; the gate signal enables the output buffer to receive data bits over a predetermined time interval. The output buffer is connected to a data transmission means such as a bus, and is gated by a second signal to place the stored information on the bus. The second signal, the message gate signal, is timed to place the information stored in the output buffer on the bus during the period beginning with the typical data bit delivery time and ending after the worst case data bit delivery time.

Abstract: The invention concerns a position measuring device used for measuring the position of a vessel equipped with three hydrophones arranged at the apexes of a triangle in relation to a transmitting beacon on the sea bed. Measuring of the differences in the travel time between the beacon and the various hydrophones as well as of the depth of the water and analogic calculating of the position of the vessel in a simple way and without approximation. Application to offshore drilling vessels.

Abstract: The disclosure describes apparatus for handling detected errors in a data processing system. First means define and locate the detected errors and second means allow the attempted reexecution of the instruction being executed when the error is detected.

Abstract: A self-test monitor and diagnostic apparatus which includes a test step counter, an error comparator apparatus, which may be a memory device loaded so as to predict the proper state of each of the lines to be monitored at each test step and which functions to detect any difference between what should be occurring at that test step and what is, in fact, occurring on the monitored line, and an error localization network which translates the detected errors into a displayable code for maintenance isolation.

Abstract: An article handling system including means for moving articles from one position to another and including computer means for controlling a plurality of functions of said article handling means including unalterable memory devices for controlling some of the functions and manually operable mechanical selectively programmable memory devices for controlling other of the functions.

Abstract: An apparatus is provided for analyzing output signals of digital devices. The apparatus comprises a plurality of comparison registers which evaluate the digital output signals, each comparison register including rotary switches for decoding the output signals under analysis. Programming switches permit to generate a function signal through at least one output channel provided in each comparison register when the output signals and the decoded value of said register are in a predetermined relationship. The operations of all comparison registers are selectively controlled by means of a logic circuit. As a result, a function signal is issued by the comparison register through a given channel in accordance with a predetermined program set by the switches and under the control of the logic circuit means, whenever a predetermined relationship exists between the output signals from the digital device under analysis and the value decoded on the comparison register.

Abstract: A system for aiming a weapon such as an antiaircraft gun at a target which includes in combination an optical sighting mechanism having a movable reticle and a movable target mark associated with the movable reticle, digital to rotational motion transducers coupled to the movable reticle and the movable target mark and a digital computer adapted to receive inputs indicative of the azimuth and elevation of the target as well as its estimated velocity and ballistic characteristics of the ammunition used. The computer is programmed to compute the flight path of the target and a lead angle based upon certain trigonometric relationships and provides a digital output to the digital-to-rotational motion transducers to position the reticle and target mark in the optical sighting mechanism.

Abstract: Apparatus for generating graphic symbols on a cathode-ray tube employs a beam control system which starts each of a plurality of parallel strokes required for each symbol at the bottom, using a programmed offset for symbols which extend below a baseline, and to otherwise move a symbol in the X and Y axes from a position routinely specified as spaced symbols are displayed in a line. The slope of the strokes for a symbol is controlled for italicizing the symbols by programming the relative magnitudes and signs of inputs to X and Y integrators which generate ramp signals added to symbol positioning signals. The beam is turned on and off during each stroke in response to a programmed and clocked bit stream of coded digital signals. The size of a symbol is controlled by programming the clock rate for the beam on-off control and the magnitudes of the inputs to the X and Y integrators.