Abstract: A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.

Abstract: An arithmetic logic register stack device is provided on a single semiconductor chip, which device comprises a building block for digital systems. The device of this invention is expandable, which enables performing operations with binary numbers greater than that with which a single device is capable of performing. Unique circuit design is provided for multiple use of connector pins to the semiconductor device, thereby allowing for an increase in the complexity of the circuits that can be integrated onto a single semiconductor chip or placed into a package with a given number of pins.

Abstract: The invention relates to a method of correcting errors, particularly double adjacent errors, which occur in a transmission path of a data handling system. A family of error correcting codes can be used to provide a similar correcting power for such errors as conventional BCH codes have for single random errors. The invention is applicable to transmission systems in which data is present in the form of a sequence of fixed length blocks.

Abstract: An auxiliary memory unit for use with electronic calculators which enables verification of a series of numeric data and function entries without requiring manual re-entry. Data and function signals generated by manual actuation of a calculator keyboard are sequentially stored in a storage device in the auxiliary memory unit during a first mode of operation, termed STORE.After a complete series of entries has been made, the stored signals are sequentially read out and displayed in the original order of entry during a second mode of operation, termed READ. The stored function signals are also read out so that the read out numeric data signals are processed by the calculator during READ.

Abstract: Apparatus for monitoring a redundant multi-channel analog system and for the forming of an undisturbed mean signal value in which all channels are connected to the inputs of a maximum value selection device and a minimum value selection device with a mean value former having as inputs the signals in all channels and the inverted extreme value signals detected by the two devices.

Abstract: A PCM recording and reproducing apparatus comprising an error detecting circuit for detecting a frame including at least one word information signal with an error, the frame being a reproduction signal read from a recording medium on which certain pulse coded information is recorded in a frame distribution system, and a compensating circuit for compensating the reproduced information signal by the use of the output signal from the error detecting circuit, thereby removing the adverse effects of information dropout in spite of a high density recording.

Abstract: An in-band signalling system for the transmission of both data and control signals through a common communications channel is disclosed. Unique means of distinguishing data bits from control bits is employed without the use of additional bandwidth over that which would be required for the data alone.A novel method for signalling includes the steps of translating the data bits into a different code set than the original, examining it for control words and if any are present, modifying or corrupting the data and thereafter combining on a time division basis the translated and/or modified data and control words over a transmission channel. To receive, data is inversely modified and control words detected. Error detection of control words is achieved by translating control words followed by their complements.

Abstract: A high-speed, low-power 1-bit adder includes a combination of current-mode switches connected in a dual tree configuration in series with respective constant current sources and summing resistors. Input operand signals select particular tree paths, thereby controlling the voltage appearing across the summing resistors and sum and carry output drivers responsive to these voltages.

Abstract: Error detection for an associative directory or translator, composed of registers, comparators, and encoder which provides a binary code representation of the location of the register at which a compare occurred, includes a random access register array which responds to the coded location information to read out binary data to be compared with the binary data utilized in the associative compare of the directory or translator.

Abstract: An image can be represented by an M .times. N array I(*,*) of image points, where each point I(i,j) over the ranges 0.ltoreq.i<M and 0.ltoreq.j<N is a value or set of values representing the color and intensity of an elemental portion of the image. A black/white image can be represented by assigning to each point I(i,j) a value of 1 or 0. Thus, I(i,j) = 1 represents a black elemental image area, while I(i,j) = 0 represents a white elemental area.Image manipulation refers to that class of image processing operations which sequentially process the points of a rectangular array I(0,0), I(0,1), . . . ,I(0,n-1), I(1,0), . . . ,I(M-1, N-1) in such a way that the resulting points must be mapped into coordinate points of the array. The image processing operations satisfying this constraint include the blanking of an image area, the combining of two images, the changing of scale of an image by a rotational amount, rotation by 90.degree. , and the creation of a mirror image.

Abstract: A system for controlling the addition of signed binary numbers represented with N bits, of the 2's complement notation, is disclosed which includes addend and augend sign control circuits, and an adder circuit comprising a carry save adder and a carry proper gate adder. The addend sign control circuit receives an operation command sign signal (B, --B, .vertline.B.vertline. or --.vertline.B.vertline.) for the addend, which designates the addend of the certain type (B, .vertline.B.vertline. or --.vertline.--B.vertline.) to be applied directly to the carry save adder and designates the addend of another type (--B, .vertline.--B.vertline. or --.vertline.B.vertline.) to be applied to the carry save adder through a 1's complementer. The augend sign control circuit functions similarly for the augend being applied to the carry save adder.

Abstract: A high-speed adder circuit capable of performing addition with binary nums in 1's complement, 2's complement or sign-magnitude formats. The adder can be made in the form of a single chip that can be assembled in multiple units to expand its capacity. There is a provision for converting minus zero to plus zero so as to prevent oscillations from occurring in the loop circuit. Also, the sum output is automatically shifted to the correct format when an overflow condition occurs.

Abstract: A digital differential analyzer circuit is provided that depending on the embodiment chosen can carry out linear, parabolic, circular or cubic interpolation. In the embodiment for parabolic interpolations, the circuit provides pulse trains for the X and Y slide motors of a two-axis machine to effect tool motion along a parabolic path. The pulse trains are generated by the circuit in such a way that parabolic tool motion is obtained from information contained in only one block of binary input data. A part contour may be approximated by one or more parabolic arcs. Acceleration and initial velocity values from a data block are set in fixed bit size registers for each axis separately but simultaneously and the values are integrated to obtain the movement along the respective axis as a function of time. Integration is performed by continual addition at a specified rate of an integrand value stored in one register to the remainder temporarily stored in another identical size register.

Abstract: An electronic key telephone system is disclosed in which connections among the station sets and telephone lines are made in a central time division switching network remote from the station sets. Each station set and line is equipped with a port circuit having an individual shift register for defining the time slot interval during which a connection may take place. To assign a time slot to a port circuit, the main controller interrogates the network to find an idle time slot and then furnishes that time slot number to the network controller. In order to save central memory and to increase system reliability, the main activity memory which stores an indication of which ports are or should be interconnected in the network need not contain any reference to the time slot number assigned for the particular connection. In order periodically to verify that actual network connections reflect the state of the activity memory, two types of audits are performed.

Abstract: A text editing system which is completely comprised of magnetic bubble domain components (or charge-coupled devices) is described. The essential parts of the system are a passive storage comprising a plurality of shift registers which are a convertible structure, i.e., they can be randomly accessed or sequentially accessed depending upon the state of a plurality of conversion switches. This provides great flexibility in entry, retrieval, and restoring. An active storage comprising a plurality of shift registers is used for various text editing functions, such as insertion of data, deletion of data, etc. In the active storage, an editing shift register is provided which implements the various text editing functions using techniques such as freezing data bits and bypassing data bits in order to change the order of the data and to close gaps which may occur in the data.

Abstract: A data alignment circuit employs a plurality of data selector circuits with each of the data selector circuits including means for receiving a plurality of data bits and control means for selecting one of the bits as an output. Each of the input bits may be connected to respective successive data selector circuits, and the control means of the data selector circuits are interconnected whereby one bit of each data selector circuit is provided in a plural bit output.

Abstract: A system for digital signal processing including a random access memory accessed by counters and used for storing and shifting signals in a fast Fourier transformer (FFT).

Abstract: A high voltage system with self-test circuitry which senses the amount of current in a high voltage line and communicates this information by means of fiber optics to control electronics which in turn communicate said information to actuator means which compensate for excessive amounts of current or notify the operator of a fault. Also the system provides a continuous and automatic self test of the communication lines by use of a clocked parity checking system.

Abstract: A sample data filter using a delta modulator to feed a shift register of which selected outputs are pulsewidth weighted. Each of the coefficient multipliers include a flip-flop fed by one of the taps of the shift register and triggered by a clock. A synchronous counter, common to each of the multipliers, is fed to a NAND gate that clears the flip-flop. Interposed between the counter and the NAND gate are a series of switches, one for each stage of the counter. The flip-flop controls a switch to a source of reference voltage and the output of this switch controlled voltage from each of the multipliers is summed and fed to a demodulator.

Abstract: The apparatus extracts samples of a fluid stream containing colloidal suspended solids at a detection station wherein the electrophoretic mobility (EM) of the colloidal suspended solids is determined. The detection station automatically measures the EM and provides such data to a computer, which computes the Zeta Potential. The computer also receives other information relating to the characteristics of the colloidal suspended solids, such as temperature, the percent of solids, and the flow rate of the fluid system. The computer is programmed to interpret the input data and to provide corrective signals to processing apparatus which automatically adjust and control the additives fed into the fluid stream to achieve automatic flocculation correction so that the agglomeration of the colloidal suspended solids in the fluid stream is optimized.