Abstract: In combination with an asynchronous detector for detecting a particular digital word within a train of signals wherein the detector samples each bit in the train a plurality of times and provides a comparison signal in response to a predetermined number of correlations between the samples and a stored word, an analog to digital converter including signal conditioning means having first and second modes of operations for converting a received analog signal to a digital signal in both modes of operation and inserting periodic error pulses in the digital signal in the first mode of operation and switch means coupled to the signal conditioning means and the detector for switching the signal conditioning means between the first and second modes of operation in response to a comparison signal from the detector.

Abstract: A simplified loop communication fault location and isolation circuit which utilizes sequences of power interruption pulses in DC power distributed on the signal lines from a master repeater to control loop signal wrap functions.

Abstract: An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations.

Abstract: An equalizer comprises a tapped delay line of a transversal filter and first equalizing means responsive to a short pseudo-noise train supplied thereto for adjusting tap gains so as to make the transversal filter output signals simulate a pseudo-noise train generated at the receiver with the pulse pattern of the supplied pseudo-noise train. Larger ones, in absolute values, of the adjusted gains are placed at the center of the delay line. Responsive to a subsequently supplied long pseudo-noise train, second equalizing means self-adaptively adjusts all tap gains. The delay line preferably comprises delay units, each for a half of a common clock interval of the supplied pseudo-noise trains and data signals.

Abstract: In a recursive (zeros and poles) filter having input and output signals y and y.sub.o and having impulse response h.sub.r apparatus and method for obtaining the convolution y.sub.o = y * h.sub.r using either the convolution integral or using the discrete Fourier transform (DFT). When using the convolution integral the apparatus first computes the impulse response h.sub.r then obtains the response y.sub.o in a convolver while when using the DFT the apparatus first computes the transfer function H.sub.r then obtains the frequency spectrum Sy.sub.o of response y.sub.o. By implementing the recursive filter as a matched clutter filter, the error normally associated with this type filter is minimized.

Abstract: A portable electronic calculator is provided with a housing carrying a first printed circuit board having the operating parts mounted thereon, i.e., keyboard, electronic arithmetic unit, and multi-digit display unit. The housing is of rectangular outline and of shallow height, and is provided at one end with a receptacle communicating with the first printed circuit board and opening at the end of the housing. An electrical supply unit is mounted on a second printed circuit board which slides into said receptacle, said two printed circuit boards having plug-and-socket connection means therebetween for automatically making and breaking connections when said second printed circuit board and electrical supply unit are inserted into or removed from said receptacle.

Abstract: A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers. The two multidigit zoned decimal numbers to be added or subtracted at any given moment are supplied to the two input sides of such binary adder by way of input modifier circuits which precondition the zone and sign fields in such numbers to enable the proper propagation of digit carries across such zone and sign fields during the performance of the addition inside the binary adder. The resulting binary bit sequence appearing at the output side of the binary adder is passed to an output modifier or corrector which causes the bits in the zone and sign field positions therein to assume the proper zone and sign code values.

Abstract: The disclosure describes an interface including data lines and address lines which address a memory. Control lines control the exchanges of data among the data lines, address lines, memory and data processing unit. A parity line provides a means of checking the accuracy of the information transmitted on the data or address lines.

Abstract: Data processing circuitry for performing two serially related arithmetic operations during one and the same machine control cycle and employing an independent zone parallel type arithmetic unit capable of simultaneously performing independent arithmetic operations in the different zones thereof. Data transfer circuitry is provided for immediately supplying the output result of a first arithmetic unit zone back to the input of a second arithmetic unit zone for immediately producing a second and different result. Such transfer circuitry is constructed to operate in an asynchronous manner so that the first result is supplied back to the input of the second arithmetic unit zone as soon as it becomes available at the output of the first arithmetic zone. Thus, a second result, which is dependent on the first result, is produced during the same machine control cycle as the first result. This data processing circuitry is particularly useful for providing storage protection for a data processor.

Abstract: A reactor trip on turbine trip inhibit control system for a nuclear power generating system which utilizes steam bypass valves. The control system inhibits a normally automatic reactor trip on turbine trip when the bypass valves have the capability of bypassing enough steam to prevent reactor trip limits from being reached and/or to prevent opening of the secondary safety pressure valves. The control system generates a bypass valve capability signal which is continuously compared with the reactor power. If the capability is greater than the reactor power, then an inhibit signal is generated which prevents a turbine trip signal from tripping the nuclear reactor.

Abstract: Recursive digital filter comprising at least two digital delay devices, a multiplying device having two inputs which are coupled to one another in a common branch point, a summing device from which a sum signal is derived the magnitude of which is at least equal to the sum of the output signal of the multiplying device, and a feedback circuit connected between the output of the summing device and the distribution point. The feedback circuit is provided with a discarding device which acts on numbers given in sign-and-magnitude representation and which by means of magnitude truncation restricts the number of bits of the numbers applied to the branch point.

Abstract: A night visual aircraft system receives flight data from an aircraft simulator, and terrain data from the gaming area data base. A computer within the night visual system organizes this image data by frame in a buffer memory according to a particular format of addresses, sequences, and bit places. The following types of image data are uniquely positioned in the format:A position vector (Vp), defining the changing position of the aircraft with respct to the terrain data origin.Rotational matrix data defining the changing attitude of the aircraft with respect to the axes of the terrain coordinate system.Initialization vectors (Vi), defining the position of certain landmark terrain lights (initial points) with respect to the position of the aircraft.Delta data, defining the position of other lights with respect to the landmark lights.String data, defining the spacing, color, intensity, and number of lights in a string of lights having equal spacing and intensity.

Abstract: Apparatus for indicating an abnormal program execution by a process controlling computer in, for example, a telecommunication system wherein the different programs, each consisting of one or more program sectors, are called for and executed within certain so-called priority levels. Each priority level includes a counter for supervising the execution of the programs on the level. This counter is stepped, for example, in its forward direction by a clock for measuring the time during which the computer works on the associated priority level and if a certain time limit is exceeded, a warning signal is obtained. For supervising the work of a certain program sector a second counter is arranged which is stepped in either direction by means of the clock and if a certain time limit is exceeded an alarm signal is obtained.

Abstract: Achieving N-key rollover by detecting the leading edge of the binary coded signal generated in bit parallel form in response to keyboard key depression and blocking the receipt of data representing a subsequently depressed key where the width of each binary bit signal is less than the interval between two successive system timing pulses which in turn is much less than the 10 millisecond or so interval between successive key operations by an operator as a result of rollover typing.

Abstract: A combinatorial digital filter apparatus utilizing a second order filter in which bits are processed simultaneously rather than serially.

Abstract: Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is by logical gating which operates selectively and on-the-fly, that is, while the sum from the output of the binary adder is being transferred to an accumulator. As a result, the same binary adder can provide the binary sum of the operands supplied to it, or the binary coded decimal sum of bcd operands, or the binary coded decimal difference of bcd operands, in a single operating cycle and without the need to recycle the sum of the operands through the adder. This single cycle correction significantly speeds up the operation of the invented microprocessor as compared to known prior art microprocessors which recycle the adder output when a binary coded decimal sum or difference is required.

Abstract: An arrangement for applying the bits of a binary coded word to the inputs of respective ones of a first plurality of reiterative digital stores in a predetermined time sequence. A further means is provided for subsequently applying a code of parity bits for the said binary word to the inputs of respective ones of a second plurality of reiterative digital stores in a predetermined time sequence. And also there is a means for causing the word and parity bits to traverse their respective stores in the same sequence.As a result, the binary data can receive a dual check for correctness.

Abstract: Apparatus for providing notification of and distinguishing among various kinds of errors in information transferred between the central processor and the peripheral units of a digital computer system by isolating the elements of such system in which certain kinds of errors can occur.

Abstract: A digital error signal generator produces a pseudorandom bit sequence having a predetermined probability density. Selective multiple pseudorandom bit densities, each having a predetermined probability density, are obtained from a single original pseudorandom bit sequence. Multiple data channels are serviced simultaneously by a single error signal generator with the probability density being individually selective for each channel.

Abstract: An analog electrical system utilizes a signal from a coke weighing system and a signal from a coke moisture gauge to correct for prior errors in hopper weighings due to delivery overshoot as well as moisture variations in prior batches of coke.