Patents Examined by Ramamohan Rao Paladugu
  • Patent number: 6062869
    Abstract: A stacked film assembly for use as wiring in a semiconductor device having a bottom film (CVD-W film) 33 and a top film (Al alloy film) 12, where the surface roughness (Ra) of the bottom film is less than 100 .ANG. and the crystal orientation of the top film formed on this surface is controlled, a CVD method for the making thereof, and a semiconductor device in which the stacked film assembly is employed. Even when there is no lattice matching of the bottom film and the top film, crystal orientation of the top film can be sufficiently controlled to provide a targeted face ((111) face with aluminum film), and in particular it will be possible to readily form a stacked film assembly having a satisfactory barrier function as well as sufficient EM resistance and with good film formation.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: May 16, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Koichi Mizobuchi, Toshihiro Sugiura
  • Patent number: 5872016
    Abstract: Optoelectronic devices such as photodetectors, modulators and lasers with improved optical properties are provided with an atomically smooth transition between the buried conductive layer and quantum-well-diode-containing intrinsic region of a p-i-n structure. The buried conductive layer is grown on an underlying substrate utilizing a surfactant-assisted growth technique. The dopant and dopant concentration are selected, as a function of the thickness of the conductive layer to be formed, so that a surface impurity concentration of from 0.1 to 1 monolayer of dopant atoms is provided. The presence of the impurities promotes atomic ordering at the interface between the conductive layer and the intrinsic region, and subsequently results in sharp barriers between the alternating layers comprising the quantum-well-diodes of the intrinsic layer.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: February 16, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: John Edward Cunningham, Keith Wayne Goossen, William Young Jan, Michael D. Williams
  • Patent number: 5707892
    Abstract: A method for fabricating a semiconductor laser diode includes the steps of forming a double hetero structured semiconductor layer on a substrate, forming a dielectric layer on the double hetero structured semiconductor layer, selectively etching the dielectric layer to expose a portion of the double hetero structured semiconductor layer, selectively removing the exposed semiconductor layer using the dielectric layer as a mask by liquid phase etching, and re growing a semiconductor layer on the etched portion by liquid phase epitaxy.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: January 13, 1998
    Assignee: LG Electronics, Inc.
    Inventors: Tae Kyung Yoo, Meoung Whan Cho, Ju Ok Seo, Shi Jong Leem, Min Soo Noh
  • Patent number: 5705403
    Abstract: A method of sensing the concentration of a doped impurity on a semiconductor in real time and a method of sensing the change of its growth rate dependent on time among the changes of the growing conditions due to doping by using a real time analysis apparatus in growing a heterostructured semiconductor by a MOCVD method. A reflecting signal during the growth by means of a real time analysis apparatus has a periodic property, an amplitude change of a reflecting signal is dependent on an absorption coefficient when an absorption exists on an epitaxial layer, an impurity concentration can be obtained by using the relation of an absorption coefficient and an impurity concentration. In addition, if each peak is independently analyzed, the respective growth rate dependent on time are measured individually, so that the reduced growth rate dependent on time of the growth rate is sensed in a carbon doped AlAs layer.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: January 6, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong-Hyeob Baek, Bun Lee, Jin-Hong Lee, Sung-Woo Choi
  • Patent number: 5693558
    Abstract: The present invention relates to a method for fabricating a semiconductor laser diode in optical communication system, having the steps for forming current blocking layers on the resulting structure of the mesa structure and then forming an opening through the current blocking layer on the mesa structure.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: December 2, 1997
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Soo Won Lee, Gyu Seog Cho, Tae Jin Kim, Kyung Seok Oh
  • Patent number: 5683935
    Abstract: The first feature of the present invention resides in that in a method of semiconductor crystallization, comprising a characteristic determining step of applying first crystallizing energy to a predetermined area of an amorphous semiconductor thin film to determine the size of an area so as to form a single crystal nucleus on the area; and a polycrystalline semiconductor thin film forming step of forming a polycrystalline semiconductor thin film from the amorphous semiconductor thin film, the polycrystalline semiconductor thin film forming step, comprises: a film forming step of forming an amorphous semiconductor thin film on the surface of a substrate; a first crystallizing step of applying first crystallizing energy at regular intervals on the area having the size determined by the characteristic determining step of the amorphous semiconductor thin film; and a second crystallizing step of applying second crystallizing energy to the amorphous semiconductor thin film to grow the crystal of the amorphous semic
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: November 4, 1997
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Yasuaki Miyamoto, Ichirou Asai
  • Patent number: 5681759
    Abstract: Method of forming a crystalline silicon film having excellent characteristics. An amorphous silicon film is formed on a substrate having an insulating surface. The amorphous film is thermally annealed at 400.degree.-620.degree. C., preferably at 520.degree.-620.degree. C., more preferably at 550.degree.-600.degree. C., for 1-12 hours. The silicon film is crystallized to a crystallinity of 0.1-99.9%, preferably 1-99%. Then, the silicon film is irradiated with UV laser radiation. Thus, the crystallinity of the silicon film is improved in a short time. Crystalline silicon films having uniform characteristics are obtained.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: October 28, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 5681758
    Abstract: A method of supplying raw material for fabricating semiconductor single crystal according to the continuously charged method provides an inventive method to overcome the problems of the raw material being charged either insufficiently or excessively, and to charge the raw material steadily. According to the inventive method, the raw material of two polysilicon bars is melted simultaneously and flows to the crucible. By calculating the difference between the weight of the growing single crystal and that of the molten raw material, the insufficiency or excess of the raw material charged is obtained, thereby inducing the equivalent regulation. Further, the coordinates of the tips of the raw material of two polysilicon bars while molten is taken to control the power of the two heaters which melt the polysilicon bars respectively for keeping the coordinates of the two tips in a constant position.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: October 28, 1997
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Yutaka Shiraishi
  • Patent number: 5679603
    Abstract: A high resistance compound semiconductor layer included in a semiconductor device including a plurality of compound semiconductor layers having different compositions includes a compound semiconductor that is vapor phase grown employing an organic metal compound including In, an organic metal compound including Al, and a hydrogenated compound or an organic metal compound including As. The high resistance compound semiconductor layer includes p type impurities having a concentration that positions the Fermi level of the compound semiconductor approximately at the center of the band gap of the compound semiconductor. Therefore, it is possible to produce a high resistance AlInAs layer that has less impurities that are diffused into an adjacent compound semiconductor layer.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: October 21, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Kimura, Takao Ishida, Takuji Sonoda
  • Patent number: 5668049
    Abstract: In a method of making a GaAs-based semiconductor laser, a fully processed wafer is cleaved, typically in the ambient atmosphere, into laser bars, the laser bars are loaded into an evacuable deposition chamber (preferably an ECR CVD chamber) and exposed to a H.sub.2 S plasma. Following the exposure, the cleavage facets are coated in the chamber with a protective dielectric (preferably silicon nitride) layer. The method can be practiced with high through-put, and can yield lasers (e.g., 980 nm pump lasers for optical fiber amplifiers) capable of operation at high power.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: September 16, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Utpal Kumar Chakrabarti, William Scott Hobson, Fan Ren, Melinda Lamont Schnoes
  • Patent number: 5668048
    Abstract: A technique for manufacturing a semiconductor device includes the steps of preparing a stepped substrate made of a group III-V compound semiconductor and having a flat surface exposing a (1 0 0) plane and a slanted surface exposing an (n 1 1)B plane, wherein is a real number of about 1.ltoreq.n, and epitaxially growing the group III-V compounds semiconductor to form an epitaxial layer on the surface of the stepped substrate while doping p- and n-type impurities, selectively at the same time or, alternatively, under conditions such that the grown epitaxial layer has an n-type region on the slanted surface and a p-type region on the flat surface.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: September 16, 1997
    Assignee: Fujitsu Limited
    Inventors: Makoto Kondo, Chikashi Anayama, Hajime Shoji
  • Patent number: 5665637
    Abstract: Provision of a novel passivation layer can result in improved reliability of semiconductor lasers having a laser cavity defined by 2 laser facets. In a preferred embodiment, the passivation layer is a zinc selenide layer (e.g., 5 nm), formed on an essentially contamination-free laser facet. More generally, the passivation layer comprises at least one of Mg, Zn, Cd and Hg, and at least one of S, Se and Te. Typically, the facets are formed by cleaving in vacuum, immediately followed by in-situ deposition of the novel passivation layer material on the facets.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: September 9, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Naresh Chand
  • Patent number: 5661075
    Abstract: A substrate (103) having a first stack of DBRs (106), an active region (118), and a second stack of DBRs (138) is provided. An etch mask (146) is formed on the second stack of DBRs (138) and etched. The second stack of DBRs (138), the active region (118), and a portion of the first stack of DBRs (106) are subsequently etched. A portion of the etch mask (146) is removed from the etch mask (146). A material layer (202, 302) is then selectively deposited on portions of the second stack of DBRs (138), the active region (118), and the first stack of DBRs (106) by either selective epitaxial over-growth or mass-transfer processes, thereby passivating the VCSEL (101).
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: August 26, 1997
    Assignee: Motorola
    Inventors: Piotr Grodzinski, Michael S. Lebby
  • Patent number: 5661077
    Abstract: Disclosed is a method for fabricating an optical integrated circuit capable of obtaining a current confinement and a maximum opto-coupling efficiency by using a simple process, in a case where an active device such as an optical waveguide and an optical amplifier. The method comprises a step for growing layers constituting the optical device over an InP substrate, a step for etching the grown layers by use of a wet etching method or a dry etching method of RIE along a plane perpendicular to a (001) plane, and a step for growing a core layer and a clad layer of the waveguide to be optically connected by use of a molecular organic chemical vapor deposition.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: August 26, 1997
    Assignees: Electronics And Telecommunications Research Institute, Korea Telecommunication Authority
    Inventors: Kwang-Ryong Oh, Ju-Heon Ahn, Jeong-Soo Kim
  • Patent number: 5661076
    Abstract: A method for non-active processing of an etched surface in a vertical-cavity surface-emitting laser diode is provided. In order to obtain a stable single fundamental transverse mode, at a low temperature of 100 to 300 degrees, an amorphous GaAs is deposited on a surface of an etched active layer and an etched cavity. Also, a bottom emitting laser is provided which is formed by, with the metal electrode as a mask, etching the top mirror layer and the active layer, depositing the amorphous GaAs onto the etched portion and planarizing the deposited GaAs layer and depositing p-type metal pad over the amorphous GaAs around the formed laser device. Also, a top emission type laser is provided which is formed by, with a photoresist as a mask, etching the top mirror layer and the active layer, planarizing the GaAs layer and depositing p-type metal pad containing a window for light emission which is made smaller than laser area over the amorphous GaAs around the formed laser device.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: August 26, 1997
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Byeung-Su Yoo, Hyo-Hoon Park, Hye-Yong Chu, Min-Soo Park
  • Patent number: 5658834
    Abstract: Active semiconductor devices including heterojunction diodes and thin film transistors are formed by PECVD deposition of a boron carbide thin film on an N-type substrate. The boron to carbon ratio of the deposited material is controlled so that the film has a suitable band gap energy. Boron carbides such as B.sub.4.7 C, B.sub.7.2 C and B.sub.19 C have suitable band gap energies between 0.8 and 1.7 eV. The stoichiometry of the film can be selected by varying the partial pressure of precursor gases, such as nido pentaborane and methane. The precursor gas or gases are energized, e.g., in a plasma reactor. The heterojunction diodes retain good rectifying properties at elevated temperature, e.g., up to 400.degree. C.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: August 19, 1997
    Assignee: Syracuse University
    Inventor: Peter A. Dowben
  • Patent number: 5658824
    Abstract: A semiconductor laser device includes: a lower cladding layer; an upper cladding layer having a bottom and a strip-shaped ridge portion projecting from the bottom; a II-VI compound semiconductor active layer interposed between the lower cladding layer and the upper cladding layer; and a burying blocking layer made of an aromatic polyamide resin formed on a bottom of the upper cladding layer so as to be in contact with sides of the stripe-shaped ridge portion.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: August 19, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigetoshi Itoh, Toshiyuki Okumura
  • Patent number: 5658825
    Abstract: InAsSb/InAsSbP/InAs Double Heterostructures (DH) and Separate Confinement Heterostructure Multiple Quantum Well (SCH-MQW) structures are taught wherein the ability to tune to a specific wavelength within 3 .mu.m to 5 .mu.m is possible by varying the ratio of As:Sb in the active layer.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: August 19, 1997
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 5656531
    Abstract: An embodiment of the present invention develops a process for forming Hemi-Spherical Grained silicon by the steps of: forming amorphous silicon from a gas source comprising at least one of dichlorosilane, disilane or trisilane, wherein the amorphous silicon comprising at least one impurity doped amorphous portion, the amorphous silicon is deposited at a deposition temperature no greater than 525.degree. C; and annealing the amorphous silicon for a sufficient amount of time and at an elevated annealing temperature, thereby transforming the amorphous silicon into the Hemi-Spherical Grained silicon.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: August 12, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Lyle D. Breiner
  • Patent number: 5654229
    Abstract: A method for providing an nonlinear, frequency converting optical QPM waveguide device by growing a first ferroelectric oxide film or layer on a second ferroelectric layer or medium wherein, in first and second embodiments, respectively, the second layer is initially provided with a periodic nonlinear coefficient pattern or a periodic pattern comprising a seed layer. During the growth of the first layer, the periodic pattern formed in the second layer, is replicated, transformed or induced into the first layer resulting in a plurality of substantially rectangular prismatic-shaped domains in the first layer having the periodic nonlinear coefficient pattern status based upon the periodic patterning of the second layer.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: August 5, 1997
    Assignee: Xerox Corporation
    Inventors: Florence E. Leplingard, John J. Kingston, Ross D. Bringans, David K. Fork, Robert G. Waarts, David F. Welch, Randall S. Geels