Abstract: A method of manufacturing a light emitting diode, which includes the steps of bringing a semiconductor substrate of p-type or n-type into contact with a growth solution at a high temperature and thereafter, lowering the temperature so as to form a monocrystalline epitaxial layer of the same type as the semiconductor substrate on the semiconductor substrate, subsequently, further lowering the above temperature to form a first monocrystalline epitaxial layer of a reverse type to the epitaxial layer on the epitaxial layer and then, cutting off the growth solution to form an epitaxial wafer as a result, a growth solution to contact the first epitaxial layer of a epitaxial wafer at a high temperature, and thereafter, the temperature is lowered to form a second monocrystalline epitaxial layer of the same kind and type as the first epitaxial layer on the first epitaxial layer.

Abstract: When compound semiconductor films are grown on an InP wafer having a surface near a (100) orientation hillocks tend to arise on the films. Off-angle wafers have been adopted for substrates in order to suppress the occurrence of hillocks. The off-angle .THETA. from a (100) plane, however, is not the sole factor for determing wheather hillocks will be formed on the film. There is a concealed parameter which determines the generation of hillocks. What induces hillocks on the growing film are the defects on the substrate itself. No hillocks originate on portions of the film that correspond to the portions of the InP wafer without dislocations. The role of the off-angle .THETA. of the substrate is preventing the influence of the dislocations from transmitting to the films. A smaller density D of the defects on the substrate allows a smaller off-angle .THETA. for suppressing the hillocks from arising.

Abstract: A semiconductor laser device in which semiconductor layers of an n-type cladding layer, a quantum well active layer 106, a p-type cladding layer, and an intermediate layer are formed on an n-type GaAs substrate in successive order, and a mixed-crystal is formed in a region except the semiconductor layers of the contact layer and the lower part of the contact layer by diffusing Si into the structure from above the intermediate layer, characterized in that the contact layer and the intermediate layer are made of n-type or nonconductive semiconductor material, and a p-type low-resistance region, formed by diffusing Zn into the structure from above the contact layer, is profiled so as not to overlap with the mixed-crystal region formed by Si diffusion.

Abstract: A method of manufacturing a quantum device such as a coupled quantum boxes device are disclosed. The quantum device comprises: a semiconductor substrate; a plurality of box portions made of a first semiconductor; and a layer made of a second semiconductor provided on circumferences of the box portions, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor. The manufacturing method comprises the steps of: making a plurality of box portions of a first semiconductor on a semiconductor substrate; and covering circumferences of the box portions with a layer of a second semiconductor, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor.

Abstract: A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 2

Abstract: A process for fabricating a multilayer crystalline structure of nitrides of metals from group III of periodic table including GaN, AlN and InN is provided. The process includes the steps of heating a group III metal (26) to a temperature T1 under an equilibrium nitrogen pressure while maintaining group III metal nitride stability to form a first crystal layer of the group III metal nitride. Thereafter the method includes the step of forming a second crystal layer (28) of the group III metal nitride by decreasing the nitrogen pressure such that the second crystal layer grows on the first layer with a growth rate slower than the growth rate of the first layer at a temperature T2 not greater than temperature T1. The second layer (28) grows on at least a portion of the first layer at a predetermined thickness under the new nitrogen pressure.

Abstract: An epitaxial growth system comprises a housing around an epitaxial growth chamber. A substrate support is located within the growth chamber. A gallium source introduces gallium into the growth chamber and directs the gallium towards the substrate. An activated nitrogen source introduces activated nitrogen into the growth chamber and directs the activated nitrogen towards the substrate. The activated nitrogen comprises ionic nitrogen species and atomic nitrogen species. An external magnet and/or an exit aperture control the amount of atomic nitrogen species and ionic nitrogen species reaching the substrate.

Abstract: A low temperature ion-beam assisted deposition process, comprising the steps of cleaning at least one substrate, subjecting the substrate to a vacuum of at least 2.times.10.sup.-4 Torr, heating the substrate to a temperature of at least 280.degree. C., and directing an ion beam at the substrate, wherein the ion beam comprises ion-associated gas molecules of Si or Ge, so as to grow a thin epitaxial film of Si or Ge on the substrate.

Abstract: Heteroepitaxial growth of phosphorus-containing III/V semiconductor material (e.g., InGaAsP) on a non-planar surface of a different phosphorus-containing III/V semiconductor material (e.g., InP) is facilitated by heating the non-planar surface in a substantially evacuated chamber to a mass-transport temperature, and exposing the surface to a flux of at least phosphorus form a solid phosphorus source. This mass-transport step is followed by in situ growth of the desired semiconductor material, with at least an initial portion of the growth being done at a first growth temperature that is not greater than the mass transport temperature. Growth typically is completed at a second growth temperature higher than the first growth temperature. A significant aspect of the method is provision of the required fluxes (e.g., phosphorus, arsenic, indium, gallium) from solid sources, resulting in hydrogen-free mass transport and growth, which can be carried out at lower temperatures than is customary in the prior art.

Abstract: The present invention develops a process for forming hemi-spherical grained silicon storage capacitor plates by the steps of: forming a silicon layer over a pair of neighboring parallel conductive lines, the silicon layer making contact to an underlying conductive region; patterning the silicon layer to form individual silicon capacitor plates; exposing the silicon capacitor plates to a fluorine based gas mixture during an high vacuum annealing period, thereby transforming the silicon capacitor plates into the semi-spherical grained silicon capacitor plates; conductively doping the hemi-spherical grained silicon capacitor plates; forming a capacitor dielectric layer adjacent and coextensive the semi-spherical grained silicon capacitor plates; and forming a second conductive silicon layer superjacent and coextensive the capacitor dielectric layer.

Abstract: A method for making a set of surface-emitting laser diodes comprises the making of reflectors by the epitaxial growth of at least one semiconductor material through a mask having apertures with inclined flanks. This method leads to the obtaining of the Bragg reflectors obtained in situ, removing the need for the ion etching of a semiconductor substrate followed by a phase for the conditioning of the surface of the sample before the preparation of the desired laser structure.Application: optical power source.

Abstract: A photoelectric conversion device having a photoelectric conversion section and a transistor for transferring or amplification of the photoelectric conversion signal or an accumulating section of a photo carrier. The photoelectric conversion section and the transistor or the accumulating section have common semiconductor layer.

Abstract: A micromechanical sensor includes a support of silicon substrate having an epitaxial layer of silicon applied on the silicon substrate. A part of the epitaxial layer is laid bare to form at least one micromechanical deflection part by an etching process. The bared deflection part is made of polycrystalline silicon which has grown in polycrystalline form during the epitaxial process over a silicon-oxide layer which has been removed by etching. In the support region and/or at the connection to the silicon substrate, the exposed deflection part passes into single crystal silicon. By large layer thicknesses, a large working capacity of the sensor is possible. The sensor structure provides enhanced mechanical stability, processability, and possibilities of shaping, and it can be integrated, in particular, in a bipolar process or mixed process (bipolar-CMOS, bipolar-CMOS-DMOS).

Abstract: A method for manufacturing a thin film transistor having a crystalline silicon layer as an active layer comprises the steps of disposing a solution containing a catalyst for promoting a crystallization of silicon in contact with an amorphous silicon film, crystallizing the amorphous silicon at a relatively low temperature and then improving the crystallinity by irradiating the film with a laser light. The concentration of the catalyst in the crystallized silicon film can be controlled by controlling the concentration of the catalyst in the solution.

Abstract: A novel process for depositing amorphous silicon has been described. The process features the homogeneous reaction of, decomposition of SiH2 and deposition of amorphous silicon, in a horizontal LPCVD reaction chamber. The SiH2 is produced by initially breaking down SiH4 in a heated autoclave apparatus, and then transferring the SiH2 to the LPCVD system through heated feed lines. This homogeneous process results in excellent thickness and resistivity uniformity for wafers placed along the horizontal axis of the LPCVD chamber.

Abstract: An inductively coupled plasma chamber having a capacitor electrode during cleaning of the plasma chamber.

Abstract: In the method of the subject invention, a coating of AlN or a coating of SiC is grown in situ in the MOCVD or MOMBE reaction chamber to cover all surfaces therein. There is thus formed a stable layer on these surfaces that prevents oxygen and other impurities originally within the reaction chamber from reacting with the semiconducting layer to be grown.

Abstract: A blue, green or blue-green stripe-geometry II/VI semiconductor injection laser utilizing a Zn.sub.1-u Cd.sub.u Se active layer (quantum well) having Zn.sub.1-x Mg.sub.x S.sub.y Se.sub.1-y cladding layers and ZnS.sub.z Se.sub.1-z guiding layers is fabricated on a GaAs substrate. The stripe-geometry configuration is obtained by ion implanting a dopant such as Nitrogen or Oxygen into the structure to form blocking layer portions of higher resistivity in the second cladding layer and the second guiding layer. These blocking layer portions are positioned on both sides of, and thereby define, a stripe-shaped lateral confinement region of lower resistivity in the second cladding layer and the second cladding layer.

Abstract: A method of continuous manufacture of semiconductor integrated circuits, said method and apparatus adapted to contain the semiconductor substrate, semiconductor deposition coating processes, and etching processes within a substantially collocated series of process chambers so that the semiconductor travels from one chamber to the next without exposure to airborne impurities and contact with manufacturing personnel. The invention has particular utility in the high volume fabrication of large surface area semiconductor circuits such as active matrix liquid crystal displays. The present invention contains a roll-to-roll and continuous belt embodiment.

Abstract: A method of lithography is disclosed for making very small structures (10.sup.-6 m and smaller) on a surface such as in the manufacture of semiconductor devices. Many micron-sized or smaller droplets of a suitable material are formed on the surface, and the droplets are used for forming structures on or holes in the surface and thus are the basis for the shape and location of the structures.