Patents Examined by Ramamohan Rao Paladugu
  • Patent number: 5273933
    Abstract: In a process of manufacturing a short-wavelength-light emitting element, n- and p-type GaInAlN films are formed on a substrate made of SiC, using an MOCVD method. (CH.sub.3).sub.3 SiN.sub.3 is used as raw material for nitrogen. The films are grown at a relatively low temperature and the amount of nitrogen doped in the films is increased.
    Type: Grant
    Filed: July 23, 1992
    Date of Patent: December 28, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Toshihide Izumiya, Yasuo Ohba
  • Patent number: 5272108
    Abstract: A gallium nitride semiconductor light-emitting device comprising: a substrate of semiconductor or insulator; an N layer of n-type gallium nitride semiconductor (Al.times.Ga.sub.1-x N:0.ltoreq..times..ltoreq.1); an I layer of semiinsulating gallium nitride semiconductor (Al.sub.x Ga.sub.1-x N:0.ltoreq..times..ltoreq.1); a first electrode formed on the I layer; a low-resistance region extending from the first electrode through the I layer at least to the N layer and formed by diffusion of the material of the first electrode; and a second electrode formed on the I layer isolatedly from the first electrode.
    Type: Grant
    Filed: February 26, 1992
    Date of Patent: December 21, 1993
    Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyoda Gosei Co., Ltd.
    Inventor: Takahiro Kozawa
  • Patent number: 5272096
    Abstract: A layer of silicon carbide (33, 38, 41) is utilized in forming a bipolar transistor (30, 40). The transistor (30, 40) is formed on a substrate (31, 32) that has a single crystal silicon surface. The layer of silicon carbide (33, 38, 41) is epitaxially formed on the single crystal silicon surface. Thereafter, a layer of silicon (34) is epitaxially formed on the layer of silicon carbide (33, 38, 41). The silicon carbide (33, 38, 41) functions as an active transistor layer or alternately is within the transistor's depletion region.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: December 21, 1993
    Assignee: Motorola, Inc.
    Inventors: Edouard D. de Fresart, Hang M. Liaw
  • Patent number: 5270246
    Abstract: When an n-type semiconductor layer is formed on a p-type semiconductor layer in a device such as a semiconductor multi-layer film, the n-type semiconductor layer is formed by adding a p-type dopant as well as an n-type dopant simultaneously. In a double heterostructure semiconductor laser including an AlGaInP active layer and AlGaInP cladding layers, when an n-type current blocking layer is formed on the p-type cladding layer, the n-type current blocking layer is formed by adding a p-type dopant as well as an n-type dopant simultaneously.
    Type: Grant
    Filed: June 17, 1992
    Date of Patent: December 14, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaya Mannou, Kiyoshi Onaka
  • Patent number: 5270225
    Abstract: A resonant tunneling semiconductor device having two large bandgap barrier layers (12, 14) separated by a quantum well (13) is provided. The two barriers (12,14) and the quantum well (13) are formed between first and second semiconductor layers (11, 16) of a first conductivity type. A monolayer (17) of material having a different bandgap than the quantum well material is provided in the quantum well thereby lowering the ground state energy level of the quantum well. Alternatively, monolayers (18, 19) having a different bandgap than that of the first and second semiconductor layers (11, 16) are formed in the first and second semiconductor layers, respectively, outside of the quantum well (13).
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: December 14, 1993
    Assignee: Motorola, Inc.
    Inventors: Herbert Goronkin, Jun Shen, Saied Tehrani
  • Patent number: 5270245
    Abstract: A method of forming a III-V semiconductor device (10, 20) utilizes a III-V semiconductor substrate (11) having a plurality of III-V semiconductor layers (12, 14, 15, 16, 17). A pattern layer ( 19, 24) is formed on the plurality of layers (12, 14, 15, 16, 17). The plurality of III-V semiconductor layers (12, 14, 15, 16, 17) is etched with an isotropic etch that does not etch the pattern layer (19, 24). The isotropic etch undercuts the pattern layer (19, 24) and exposes an area for forming ohmic contacts on the plurality of III-V semiconductor layers. The pattern layer (19, 24) is used as a mask while depositing ohmic contact material (22, 23, 28) onto the area for forming ohmic contacts.
    Type: Grant
    Filed: November 27, 1992
    Date of Patent: December 14, 1993
    Assignee: Motorola, Inc.
    Inventors: Craig A. Gaw, Chan-Long Shieh
  • Patent number: 5270266
    Abstract: A method of adjusting the temperature of a semiconductor wafer comprising mounting and attracting the wafer on a susceptor in a process chamber, exhausting and decompressing the process chamber, controlling the temperature of the wafer to become equal to a process temperature while cooling or heating the susceptor, supplying process gas into the chamber to process the wafer with this process gas, and introducing CF.sub.4 gas into interstices between the wafer and the susceptor through the susceptor to allow heat exchange to be achieved between them. CF.sub.4 gas includes same components as at least some of those of the process gas and it is more excellent in heat transmitting characteristic than helium gas. Even when CF.sub.4 gas is leaked into a process area, therefore, any influence is not added to the process.
    Type: Grant
    Filed: December 10, 1992
    Date of Patent: December 14, 1993
    Assignee: Tokyo Electron Limited
    Inventors: Yoshihisa Hirano, Yoshifumi Tahara, Isahiro Hasegawa, Keiji Horioka
  • Patent number: 5268006
    Abstract: A method for manufacturing semiconductor-type laminated ceramic capacitors with a grain boundary-insulated structure including the steps of calcinating starting material of mixed powder in air or in nitrogen atmosphere after grinding, mixing and drying the mixed powder; forming raw sheets; printing a pattern of inner electrode paste on the surface of the raw sheets; calcinating the laminated body in air; sintering the laminated raw sheets in reducing atmosphere or in nitrogen atmosphere after calcination; re-oxidizing in air after sintering; and covering the edges of sintered ceramic sheets with outer electrode paste and baking after re-oxidation, terminals of inner electrodes being exposed to the edges, wherein: the starting material of mixed powder comprises a material of the composition Sr.sub.(1-x) Ba.sub.x TiO.sub.3 containing excess Ti to make a final molecular ratio of Ti to Sr.sub.(1-x) Ba.sub.x in the range of 0.95.ltoreq. Sr.sub.(1-x)Ba.sub.x /Ti< 1.00 (where x is in the range of 0< x.ltoreq.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: December 7, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Iwao Ueno, Yasuo Wakahata, Kimio Kobayashi, Kaori Okamoto, Akihiro Takami
  • Patent number: 5268327
    Abstract: A method for manufacturing, by chemical depostion from the vapor phase, epitaxial composites comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium alluminum arsenide (GaAlAs) on single crystal silicon substrates.
    Type: Grant
    Filed: May 19, 1992
    Date of Patent: December 7, 1993
    Assignee: Advanced Energy Fund Limited Partnership
    Inventor: Stanley M. Vernon
  • Patent number: 5268328
    Abstract: A method of fabricating a semiconductor laser includes successively forming on a semiconductor substrate by crystal growth an active waveguide comprised of a compound semiconductor comprising a Group V element phosphorus, a thin-film layer comprised of a first-conductivity type compound semiconductor comprising a Group V element arsenic and a current blocking layer comprised of a second-conductivity type compound semiconductor comprising a Group V element arsenic. A mask is formed for selectively etching the current blocking layer in the form of a stripe. A buffer-etching step is formed on both the current blocking layer and the mask to expose a surface of the current blocking layer and the thin-film layer, the surface including a Group V element arsenic. An outer cladding layer comprising a first-conductivity type compound semiconductor having a Group V element arsenic is formed on the current blocking layer and the thin-film layer in an atmosphere having a Group V element arsenic.
    Type: Grant
    Filed: December 16, 1992
    Date of Patent: December 7, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Mori, Masaya Mannoh, Satoshi Kamiyama, Kiyoshi Ohnaka
  • Patent number: 5266524
    Abstract: A method of manufacturing a semiconductor device whereby a layer (3) containing aluminium is deposited by means of a sputter deposition process on a surface (1) of a semiconductor body (2) which is placed on a holder (21) in a reaction chamber (20). The semiconductor body (2) is cooled down to a temperature below 150 K. during the deposition process. A smooth, flat layer with a good step coverage is deposited in this way.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: November 30, 1993
    Assignee: U.S. Philips Corp.
    Inventor: Robertus A. M. Wolters
  • Patent number: 5266079
    Abstract: The elements of the present invention are used for circuits in electronic devices and the objective is to absorb the noises and surges occurring in the circuits. In order to achieve the above objective, the present invention discloses a method for manufacturing a ceramic capacitor having varistor characteristics comprising the steps of; adding a sintering accelerant mainly forming a liquid phase at a high temperature, a semiconducting accelerant that can form a solid solution with perovskite type oxides, a control agent to control the grain growth for porous sintering and a forming agent to form a grain boundary depletion layer which also functions as a control agent to control the grain growth, to perovskite type oxides powder made of the materials of SrTiO.sub.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: November 30, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Atsushi Iga
  • Patent number: 5264040
    Abstract: A rapid switching rotating disk reactor has an elongated injector for injecting an inert gas into the chamber of a rotating disk reactor. The nozzle of the injector is proximate to the center of the rotating wafer for the purpose of providing an inert gas flow to produce an inert gas boundary layer above the wafer. Whenever the environment of the chamber is to be changed by an introduction of another fluid medium, the injector is activated to provide an inert boundary layer atop the semiconductor wafer, wherein any processing caused by the reactive gases in the chamber is prevented from occurring. Once the chamber is filled with the subsequent fluid medium, the injector is turned off in order for the next processing to commence.
    Type: Grant
    Filed: November 17, 1992
    Date of Patent: November 23, 1993
    Assignee: Sematech, Inc.
    Inventor: Franz T. Geyling
  • Patent number: 5264397
    Abstract: A method for activating the zinc dopant in an active layer of a Group III/Group V semiconductor device comprises forming a layer of zinc doped Group III/Group IV material, and thereafter annealing the layer at a predetermined temperature and for a predetermined time sufficient to convert inactive zinc in the layer to acceptor zinc. In a preferred embodiment of the invention, a method for activating zinc dopant in the active layer of an InP-InGaAsP double heterostructure comprises annealing the active layer at a temperature of about 625.degree. C. for at least about 190 seconds which converts inactive zinc to acceptor zinc without substantially decreasing the total zinc in the active layer. In another preferred embodiment, a method for increasing the power output of InP-InGaAsP optoelectronic semiconductor device, such as a laser or an LED having a zinc doped active layer, comprises annealing the active layer of the semiconductor device at a temperature of about 625.degree. C. for at least about 190 seconds.
    Type: Grant
    Filed: February 15, 1991
    Date of Patent: November 23, 1993
    Assignee: The Whitaker Corporation
    Inventors: Shwu L. Lin, John D. Kulick, Randall B. Wilson
  • Patent number: 5260230
    Abstract: According a method of manufacturing a buried heterostructure semiconductor laser, an active layer and a p-type cladding layer are sequentially deposited on an n-type group III-V semiconductor layer by metalorganic vapor phase epitaxy. A surface of the deposited layer is masked in a stripe shape, and the cladding layer, the active layer, and the semiconductor layer are selectively and partially etched to form a mesa structure. A p-type current blocking layer, an n-type current confining layer containing a group VI dopant having a concentration of not less than 5.times.10.sup.18 atoms.multidot.cm.sup.-3, a p-type cladding layer, and a p-type cap layer are sequentially deposited on an entire upper surface of the mesa structure by the metalorganic vapor phase epitaxy.
    Type: Grant
    Filed: July 7, 1992
    Date of Patent: November 9, 1993
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Yasuhiro Kondo
  • Patent number: 5260231
    Abstract: A semiconductor laser device is disclosed which emits laser light from a facet. The semiconductor laser device comprises a multi-layered structure formed on a semiconductor substrate, the multi-layered structure having an AlGaAs active layer for laser oscillation, and a protective film formed on the facet, wherein a film containing sulfur is provided between the facet and the protective film.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: November 9, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidenori Kawanishi, Taiji Morimoto, Shinji Kaneiwa, Hiroshi Hayashi, Nobuyuki Miyauchi, Seiki Yano, Mitsuhiro Matsumoto, Kazuaki Sasaki, Masaki Kondo, Takehiro Shiomoto, Saburo Yamamoto
  • Patent number: 5258091
    Abstract: An X-ray window having a diamond X-ray transparent film, diamond reinforcing crosspieces and a substrate on which the diamond X-ray transparent film has been grown. As reinforcing crosspieces are made of diamond, no thermal stress is generated between the X-ray transparent film and the crosspieces. This mask excels in flatness, transmittance of X-rays, and strength.
    Type: Grant
    Filed: May 12, 1992
    Date of Patent: November 2, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takahiro Imai, Naoji Fujimori
  • Patent number: 5258326
    Abstract: The present invention is directed to a method of fabricating quantum devices such as quantum boxes and quantum wires measuring as small as several tens of nanometers utilizing selectivity based on crystal plane orientation. A substrate is provided with a surface having an (100) crystal plane orientation. A first layer of a semiconductor material, such as AlGaAs or GaAs, is epitaxially grown on the surface of the substrate as a trapezoid having a (100) crystal plane orientation top surface and a (111)B crystal plane orientation side surface around the top surface. An As.sub.2 beam is used for MBE growth of a second layer of GaAs or InGaAs on the (100) surface of the first layer. The growth of the third layer on the (111)B crystal plane orientation region is prevented by an As trimer structure such that growth only takes place at the (100) crystal plane orientation region.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: November 2, 1993
    Assignee: Eastman Kodak Company
    Inventors: Mitsukata Morishima, Toshiroh Hayakawa
  • Patent number: 5256164
    Abstract: A gain medium is disposed between two mirrors to form a resonant cavity. The cavity length is selected so that the gain bandwidth of the gain medium is less than or substantially equal to the frequency separation of the cavity modes and such that a cavity mode frequency falls within the gain bandwidth. A nonlinear optical material is disposed either inside or outside the cavity to generate new laser wavelengths. The nonlinear optical material may be contained in a cavity which is resonant at the microchip laser frequency. Alternatively, the microchip laser may be tuned, for example thermally or by the application of a longitudinal or transverse stress, to the frequency of the resonant cavity. The laser is optically pumped by any appropriate source such as a semiconductor injection laser or laser array. Suitable gain media include Nd:YAG, Nd:GSGG and Nd pentaphosphate, and suitable non-linear optical material include MqO:LiNbO.sub.3 and KTP.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: October 26, 1993
    Assignee: Massachusetts Institute of Technology
    Inventor: Aram Mooradian
  • Patent number: 5256566
    Abstract: A method for in-situ doping of deposited silicon is disclosed. The method utilizes low temperature of approximately 560.degree. C., low pressure of approximately 300 mTorr, and low phosphine to silane ratio of approximately 0.0008 to form phosphorus doped silicon. The method is manufacturable in an automated LPCVD reactor. It allows relatively uniform defect free silicon films of low resistivity and good conformality and step coverage to be deposited at sufficient deposition rates over large semiconductor wafer lots for high wafer throughput.
    Type: Grant
    Filed: May 8, 1991
    Date of Patent: October 26, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Dane E. Bailey