Patents Examined by Ramamohan Rao Paladugu
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Patent number: 5256596Abstract: VCSELs including a central active layer with upper and lower mirror stacks wherein a circular trench is formed in one mirror stack to define a lasing area. The trench reduces reflectivity to prevent lasing outside the operating area and a deep beryllium implant in either of the mirror stacks, along with the trench, confines current distribution to maximize power output and efficiency. A transparent metal contact is used as a top contact in one embodiment.Type: GrantFiled: March 26, 1992Date of Patent: October 26, 1993Assignee: Motorola, Inc.Inventors: Donald E. Ackley, Chan-Long Shieh
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Patent number: 5254505Abstract: A process of forming a capacitive insulating film comprises the steps of forming a tantalum oxide film through thermochemical reaction involving organic tantalum charge gas and oxygen gas, and subsequently forming a tantalum oxide film through plasma chemical reaction involving tantalum halogenide charge gas and nitrous oxide (N.sub.2 0) gas, said steps being performed in the same apparatus.Type: GrantFiled: September 3, 1991Date of Patent: October 19, 1993Assignee: NEC CorporationInventor: Satoshi Kamiyama
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Patent number: 5254207Abstract: Material and impurity gases are introduced into a crystal growth chamber to grow a crystal film on a GaAs substrate. A light beam emitted from a variable-wavelength light source is applied to the crystal film being grown on the substrate while varying the wavelength of the light beam. The dependency, on the wavelength of the light beam, of the intensity of light reflected by the crystal film is measured, and an optimum wavelength is selected for measurement depending on the type of molecules adsorbed while the crystal film is being grown. Light is then applied at the optimum wavelength to the crystal film being grown, and a time-dependent change in the intensity of light reflected by the crystal film is measured. The rate at which the material gases are introduced into the crystal growth chamber is adjusted to control the growth rate of the crystal film, the composition ratio of a mixed crystal thereof, and the density of the impurity therein.Type: GrantFiled: November 30, 1992Date of Patent: October 19, 1993Assignees: Research Development Corporation of Japan, Jun-ichi Nishizawa, Zaidan Hojin, Handotai Kenkyu ShinkokaInventors: Jun-ichi Nishizawa, Toru Kurabayashi
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Patent number: 5252513Abstract: The present invention is an apparatus and method for providing detection of a laser output on a semiconductor wafer. A laser cavity and a detection cavity are formed on a semiconductor wafer in parallel such that light emitted laterally from the laser cavity is detected by the detection cavity. The amount of light detected can then be transformed into data, which in turn can be used to control the output of the laser.Type: GrantFiled: June 12, 1991Date of Patent: October 12, 1993Assignee: Xerox CorporationInventors: Thomas L. Paoli, G. A. N. Connell, Donald R. Scifres, Robert L. Thornton
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Patent number: 5252514Abstract: A process for the production of a low-loss optical waveguide in an epitaxial silicon film is employed to form a silicon structural element with integrated electronic components in a silicon substrate. Between the silicon substrate and the epitaxial silicon film is an insulating film. The epitaxial film consists of silicon-on-insulator (SOI) material, which is an uncommon material. In order to carry out this process relatively cheaply, a lightly doped epitaxial silicon film is applied to the silicon substrate. A substance germanium and having a refractive index with a real component higher than that of silicon is diffused into the epitaxial silicon film.Type: GrantFiled: March 2, 1992Date of Patent: October 12, 1993Assignee: Siemens AktiengesellschaftInventor: Bernd Schuppert
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Patent number: 5244828Abstract: The method of fabricating a quantum device of the invention includes the steps of: forming a quantum dot having side faces on a first insulating layer; forming a second insulating layer which can function as a tunnel film, on at least the side faces of the quantum dot; depositing a non-crystal semiconductor layer on the first insulating layer so as to cover the quantum dot; removing at least a portion of the non-crystal semiconductor layer which is positioned above the quantum dot; single-crystallizing a predetermined portion of the non-crystal semiconductor layer which is in contact with the second insulating layer; and forming a quantum wire which includes the single-crystallized semiconductor portion and the quantum dot, on the first insulating layer.Type: GrantFiled: August 25, 1992Date of Patent: September 14, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Okada, Yasuaki Terui, Juro Yasui, Yoshihiko Hirai, Masaaki Niwa, Atsuo Wada, Kiyoshi Morimoto
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Patent number: 5242847Abstract: Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.Type: GrantFiled: July 27, 1992Date of Patent: September 7, 1993Assignee: North Carolina State University at RaleighInventors: Mehmet C. Ozturk, Douglas T. Grider, Mahesh K. Sanganeria, Stanton P. Ashburn
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Patent number: 5242857Abstract: In a semiconductor buried heterostructure laser having a mesa (2, 3, 4) and confinement layers (5, 6, 7) on a substrate (12), at least the lowermost of the confinement layers (5, 6, 7) is substantially planar up to the mesa. This is achieved by MOVPE growth of InP against lateral surfaces of the mesa (2, 3, 4) which are defined by distinct crystallographic planes of the material of the mesa. In particular (111) B InP planes are used. The laser is particularly for use in the field of optical communications.Type: GrantFiled: January 22, 1992Date of Patent: September 7, 1993Assignee: British Telecommunications public limited companyInventors: David M. Cooper, Andrew W. Nelson, Simon Cole, Ian F. Lealman, William J. Devlin
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Patent number: 5242839Abstract: The present invention relates to an integrated photoelectric receiving device in which a PIN-type photodetector and a junction field effect transistor (FET) are integrated in a single chip. The photoelectric receiving device comprises a photodetector having a n-channel layer, an etching stopper layer and an absorption layer formed on a semi-dielectric substrate, the n-channel layer, the etching stopper layer and the absorption layer being formed in a reverse mesa shape and the substrate being etched by a predetermined depth; a transistor having a n-channel layer, an etching stopper layer and a p-type InP layer sequentially formed on the non-etched portion of the semi-insulator substrate, the p-type InP layer having an absorption layer formed thereon in a reversedmesa shape. Also, the invention contemplates a method of manufacturing the device.Type: GrantFiled: November 25, 1992Date of Patent: September 7, 1993Assignee: Electronics and Telecommunications Research InstituteInventors: Kwang-Ryong Oh, Yong-Tak Lee
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Patent number: 5238877Abstract: A method for fabricating a conformal optical waveguide on a semiconductor bstrate which results in an improved conformal processing method of producing ferroelectic ceramic waveguides that is integratable with conventional electronic and optoelectronic devices. First, a patterning of a desired waveguide configuration is made on a desired semiconductor substrate. A conformal confinement layer is fabricated in the pattern of the desired waveguide configuration on the semiconductor substrate. The conformal confinement layer has an index of refraction. Next, the method calls for a placing of a sol-gel waveguide precursor in the conformal confinement layer. Next the spin casting of a sol-gel waveguide precursor shapes a sol-gel conformal waveguide layer in the conformal confinement layer on the semiconductor substrate.Type: GrantFiled: April 30, 1992Date of Patent: August 24, 1993Assignee: The United States of America as represented by the Secretary of the NavyInventor: Stephen D. Russell
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Patent number: 5236874Abstract: A method is provided for forming a material layer in a semiconductor device using liquid phase deposition. A material layer such as a metal layer, a dielectric layer, a semiconductor layer or a superconducting layer is deposited by the liquid-phase thermal decomposition of a metal-organic precursor dissolved in an anhydrous organic solvent. The organic solvent has a chemical polarity corresponding to the selected metal-organic precursor and has a normal boiling point above the decomposition temperature of the selected precursor. As a result of few restrictions on the range of precursor physical properties, the present invention enables the use of a wide variety of molecular compositions which can be used for the formation of an equally wide variety of material layers. In one embodiment of the invention, a semiconductor substrate is subjected to a liquid mixture comprising a metal-substituted heterocyclic acetylacetonate precursor dissolved in tetradecane (b.p. 254.degree.C.).Type: GrantFiled: March 8, 1991Date of Patent: August 17, 1993Assignee: Motorola, Inc.Inventor: Faivel S. Pintchovski
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Patent number: 5234862Abstract: A thin film deposition method consists of depositing a thin film on a wafer by supplying a reactant gas molecules toward and onto the wafer within a vacuum vessel or chamber. The pressure within the vacuum vessel is set to the pressure under which the mean free path (d) of the molecules contained in the supplied reactant gas can be longer than the shortest distance (L) between the wafer and the wall of the vacuum vessel exposed to the vacuum side, or d>L. The temperature of the wafer is set to the temperature (T sub) at which the reactant gas can cause substantially the thermally decomposing reaction. The temperature of the vacuum side-exposed wall of the vacuum vessel (T wall) is set to a temperature range having the lower limit higher than the temperature (T vap) at which the saturated vapor pressure can be maintained to be equal to the partial pressure of the molecules contained in the reactant gas, and having the upper limit lower than the temperature of the wafer (T sub), or T vap<T wall<T sub.Type: GrantFiled: September 9, 1991Date of Patent: August 10, 1993Assignees: Anelva Corp., NEC Corp.Inventors: Ken-ichi Aketagawa, Junro Sakai, Toru Tatsumi, Shun-Ichi Murakami, Hiroyoshi Murota
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Patent number: 5232547Abstract: A semiconductor wafer (11) with a lattice mismatched film (12) on its upper surface is placed on a flat support surface (15). A laser beam (13, 23, 24, 26, 27) is directed onto the film (12). Curvature of the semiconductor wafer caused by the film (12) is measured simultaneously with film thickness based on characteristics of the reflected laser beam (23, 24, 26, 27). Strain within the film (12) is calculated from the curvature of the semiconductor wafer, film composition is calculated from the stress and thickness based on known properties of the film (12).Type: GrantFiled: July 1, 1992Date of Patent: August 3, 1993Assignee: Motorola, Inc.Inventors: Clifford I. Drowley, Marco Racanelli, Phillip H. Williams