Abstract: P-type impurity induced layer disordering (IILD) in compound semiconductor structures or multilayer semiconductor material structures is produced by providing a source of a disordering agent during annealing multiple layers of III-V semiconductor material at high temperature under Group III material-rich conditions. For example, diffusion of silicon causes impurity induced layer disordering of GaAs/AlGaAs quantum well structures. By diffusing the silicon under gallium-rich conditions or from a gallium-rich source layer, the desired disordering is achieved simultaneously with p-type doped material. Silicon is an amphoteric dopant in gallium arsenide. Silicon occupies the gallium and arsenic sites with comparable frequencies with predominantly occupied site determined by the arsenic and gallium chemical potentials. Diffusion of silicon causes impurity induced layer disordering (IILD) of GaAs/AlGaAs quantum well structures.

Abstract: A method for preparing a semiconductor member comprising steps of: making a silicon substrate porous; forming a non-porous silicon monocrystalline layer on the porous silicon substrate at a first temperature; bonding a surface of the non-porous silicon monocrystalline layer on to another substrate having an insulating material on the surface thereof; etching the porous silicon by removing the porous silicon of the bonded substrate by chemical etching; and forming a monocrystalline silicon layer on the non-porous silicon monocrystalline layer by epitaxial growth at a second temperature higher than the first temperature.

Abstract: A compound semiconductor device and a process for manufacturing it is disclosed. The process comprises the steps of forming a first conduction type first clad layer, a first conduction type or second conduction type activated layer, a second conduction type second clad layer, and a second conduction type cap layer upon a first conduction type semiconductor substrate, forming a first conduction type electrode and a second conduction type electrode, and forming a rectangular pole shaped laser diode, a triangular pole shaped detecting photo-diode, and a triangular pole shaped receiving photo-diode by carrying out a single round of anisotropic etching. According to the present invention, the high density can be easily realized, so that the power consumption and the manufacturing cost can be saved.

Abstract: A method for epitaxially growing a II-VI compound semiconductor according to this invention comprises the steps of epitaxially growing a GaAs.sub.x Se.sub.1-x layer on a GaAs substrate and epitaxially growing a ZnSe layer or a compound semiconductor layer including ZnSe on the GaAs.sub.x Se.sub.1-x layer. This method provides a II-VI compound semiconductor in which a strain caused by a lattice mismatch is prevented and the hetero interface is excellent.

Abstract: A semiconductor material having a disordered structure consists of a semiconductor material on which epitaxial growth is possible. The semiconductor material has an energy band structure constituted by one of the indirect band structure, the direct band structure, and a combination of the indirect and the direct band structures, and consists of a plurality of semiconductor layers. The semiconductor layer is orderly arranged along its surface and disorderly arranged along its thickness direction with respect to at least one of the followings the number of atomic or molecular layers constituting the semiconductor layer, a composition of a specific molecular layer of the molecular layers, and impurity doped to the semiconductor layer.

Abstract: A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.

Abstract: A basic sample having a surface is set in an ultrahigh vacuum chamber. Atoms constituting the sample are deposited on the surface of the sample to remove vacancy-type defects. A laser beam having a predetermined wavelength and a predetermined fluence is radiated on the sample to remove adatom-type and kink-type defects, thereby producing a defect-free surface. In addition, the same material as that for a basic sample is deposited on a defect-free surface to produce a defect-free thin film.

Abstract: An improved MOS photodetector having polysilicon gate material which is made more transparent to visible light by the addition of up to 50% carbon, and preferably about 10% carbon. The surfaces of the polysilicon-carbon gates are oxidized to form a silicon dioxide dielectric layer, thus eliminating the need to deposit a separate dielectric layer for isolation of adjacent gates in an overlapping gate array. The elimination of a separate dielectric layer permits all gates to be formed directly on the substrate dielectric layer, thus providing a uniform drive voltage requirement across the array.

Abstract: A reduced pressure processing apparatus includes a processing vessel for performing predetermined processing to an object to be processed in a reduced pressure atmosphere, an exhaust mechanism, including a main exhaust system having a relatively high exhaust pressure and a sub-exhaust system having a relatively low exhaust pressure, for evacuating the processing vessel, and an oxygen gas concentration sensor for detecting an oxygen gas concentration in the processing vessel during exhaust performed by the sub-exhaust system. The oxygen gas concentration in the processing vessel is detected while the processing vessel is evacuated with a relatively low exhaust pressure. It is determined whether leakage is present or absent by confirming a detection value is a predetermined value or less within a predetermined period of time. When leakage is absent, the processing vessel is evacuated with the relatively high exhaust pressure.

Abstract: An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc telluride selenide (ZnTe.sub.x Se.sub.1-x) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc telluride selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc telluride selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc telluride selenide may be provided. An integrated heterostructure is formed by epitaxially depositing the ohmic contact on the Group II-VI device. A removable overcoat layer may be formed on the Group II-VI device to allow room temperature atmospheric pressure transfer of the device from a zinc based deposition chamber to a mercury based deposition chamber, for deposition of the ohmic contact.

Abstract: In one form of the invention, a method for the growth of an epitaxial insulator-metal structure on a semiconductor surface comprising the steps of maintaining the semiconductor surface at a pressure below approximately 1.times.10.sup.-7 mbar, maintaining the semiconductor surface at a substantially fixed first temperature between approximately 25.degree. C. and 400.degree. C., depositing an epitaxial metal layer on the semiconductor surface, adjusting the semiconductor surface to a substantially fixed second temperature between approximately 25.degree. C. and 200.degree. C., starting a deposition of epitaxial CaF.sub.2 on the first metal layer, ramping the second temperature to a third substantially fixed temperature between 200.degree. C. and 500.degree. C. over a time period, maintaining the third temperature until the epitaxial CaF.sub.2 has deposited to a desired thickness, and stopping the deposition of epitaxial CaF.sub.2 on the first metal layer.

Abstract: A heterojunction device, and a method for producing the device. A gate air bridge is formed at the mesa sidewall between the active region and the gate bonding pad to lower the gate leakage current. The device has a double recessed gate to reduce local fields in the vicinity of the gate. The fabrication method uses dielectric intermediate and final passivation layers to optimize the double-recess profile and control the extension of the high-field region between the gate and the drain. This combination increases the breakdown potential of the device, but minimizes the effective gate length of the device, preserving high frequency performance.

Abstract: A new method for accurately and sequentially growing monolayers and creating new superlattice structures employing a MBE thermal source control technique employing a quasi-double beam atomic absorption background correction measurements with the beam blocked and with the beam unblocked and by calculating the concentration based on the: ##EQU1## and applying corrections for non-linear absorption curves because of comparable spectral bandwidth of the molecular beam.

Abstract: To manufacture epitaxial wafers with a smaller amount of semiconductor crystals at a lower cost by means of an efficient epitaxial growth process. An epitaxial wafer is made by forming, by means of epitaxial growth, GaAlAs layers with identical structures on both sides of a GaAs substrate wafer with the crystal plane orientation of {100}. The epitaxial wafer is then divided in the GaAs substrate wafer portion into two pieces to obtain two epitaxial wafers. To perform the epitaxial growth process, a plurality of GaAs substrate wafers are held at their edges and then the GaAs substrate wafers are placed in a Ga solution at prescribed spatial intervals. To divide the epitaxial wafer in the GaAs substrate portion into two pieces, the substrate wafer portion is cut parallel to the main surface. Or, the GaAs substrate wafer can also be removed by means of etching while the epitaxial wafer is rotated at a high speed in the etching solution.

Abstract: The present invention is directed to a method for fabricating a dual beam semiconductor laser, wherein the laser includes first and second semiconductor laser dies respectively affixed to one another while separated by intervening alignment structures. The alignment structures provide accurate placement of the dual laser beams with respect to one another while also assuring thermal isolation of the laser diodes. The fabrication method employs photolithographic techniques to accurately position the alignment structures across an entire semiconductor wafer, thereby assuring accuracy in alignment of the assembled dual beam lasers. As a result, the need for multiple-step alignment operations commonly employed in the production of multiple diode laser devices is eliminated.

Abstract: A method of depositing atoms on a substrate in which a beam of atoms is optically focused utilizing a laser beam. The laser beam is used to form a standing wave above the surface of a substrate. As the beam of atoms is passed through the standing wave, the atoms are focused by dipole force interactions. The deposition of atoms is focused into parallel lines which coincide with the minima of the standing wave. The use of two standing waves allows for focusing the atoms into discrete dots or spots. Relative movement between the substrate and the standing wave(s) allows for depositing atoms in a scanning manner. Various nanostructures can be made by the disclosed method.

Abstract: According to a method of manufacturing a semiconductor device, a monocrystal silicon layer can be formed easily without adversely affecting semiconductor elements. In the method of manufacturing the semiconductor device, a first polysilicon layer is formed on a gate oxide film layer on a silicon substrate, and then a resist is formed on a predetermined region of the first polysilicon layer. Using the resist as a mask, anisotropic etching is effected to expose the surface of the silicon substrate. Thereby, it is not necessary to form the resist directly on the gate oxide film layer, as is done in the prior art, and it is possible to prevent impurity such as sodium or phosphorus in the resist from entering the gate oxide film layer. Consequently, it is possible to prevent a disadvantage such as change of a threshold voltage of a memory cell transistor, which may be caused by the entry of impurity.

Abstract: The disclosure relates to the field of monocrystalline thin layers deposited on a substrate having an identical or a different nature, from a vapor phase. On the substrate made of monocrystalline material A, a cavity is built, determined by one face of the substrate and one face of a layer made of a material D in such a way that there can be neither nucleation nor growth on the faces exposed to the vapor phase. The growth is done from a seed made of monocrystalline material B located between two faces of the substrate and of the layer. The seed made of monocrystalline material B may be of a nature different from that of the substrate (for example, substrate=silicon and material B=GaAs) and is made, for example, by MBE or MOCVD. The material C to be made to grow is different from the material B of the seed. The material C is, for example, InP and the growth is done by VPE.

Abstract: A textured backside of a semiconductor device for increasing light scattering and absorption in a semiconductor substrate is accomplished by applying infrared radiation to the front side of a semiconductor substrate that has a metal layer deposited on its backside in a time-energy profile that first produces pits in the backside surface and then produces a thin, highly reflective, low resistivity, epitaxial alloy layer over the entire area of the interface between the semiconductor substrate and a metal contact layer. The time-energy profile includes ramping up to a first energy level and holding for a period of time to create the desired pit size and density and then rapidly increasing the energy to a second level in which the entire interface area is melted and alloyed quickly. After holding the second energy level for a sufficient time to develop the thin alloy layer over the entire interface area, the energy is ramped down to allow epitaxial crystal growth in the alloy layer.

Abstract: A method of manufacturing a closed cavity LED including forming, on a substrate, a short cavity LED with electrically conductive layers on opposite ends. Depositing a transparent conductive layer of material over one electrically conductive layer and affixing glass or a diamond film over the transparent conductive layer to define and protect a light output area. Removing the substrate and covering the top and sides of the cavity with dielectric material and contact metal. The metal being in contact with the transparent conductive layer and the other electrical contact layer. Thus, a reflector covers the cavity in all directions except the light output area to increase external efficiency.