Abstract: A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.

Abstract: An input/output board (10 to 12) address selection system selects a desired address in the pluralities of input and output boards (10 to 12) connected to a common bus (6) of an input/output interface unit (1) connected via a serial data transmission system to a main control unit (60). A programmable address translation circuit (5) is provided for deriving a slot select signal (s1 to s16) and an in-board address (BA) from an address for an input/output board accessing address which is provided from a control circuit (2) of the input/output interface unit (1). One of the input and output boards (10 to 12) is selected by the slot select signal (s1 to s16), and one of the addresses in the selected input or output board is selected by the in-board address (BA).

Abstract: An overlapped control store including a pair of memory elements, with each element in the pair storing a complete instruction set and with instructions from the elements accessed on alternate clock cycles. A mux, controlled by a control field in each instruction, is adapted to provide either a PC address or a target address to the control store. Unrestricted branches are facilitated because every instruction in the instruction set is included in both memory elements.

Abstract: A method of processing video signals to achieve a visual effect involving three-dimensional manipulation of an input image includes the use of a circuit for determining pixel address by pixel address whether in the resulting transformed image the front or the back of the input image should be displayed. The circuit comprises a device defining an incremental surface in the transformed image by at least three adjacent non-collinear pixel addresses from the transformed image, a circuit for determining from the transformed pixel addresses whether or not a vector normal to the incremental surface points towards or away from a viewing point, and a device for selecting for display at one of the transformed pixel addresses the corresponding portion of the front or the back of the input image in dependence on whether the vector points towards or away from the viewing point.

Abstract: A disk controller address register is used to address both a disk controller memory and a system memory between which data is transferred as it is stored on or retrieved from a disk storage device. A single address is provided to the address register which then develops other addresses needed in the data transfer between the two memories.

Abstract: According to an image memory address assignment system, a frame memory is divided into a plurality of blocks. Upper bits of the address of the frame memory constitute a block address, and lower bits constitute an intrablock address. The block address is supplied to an address converter. The address converter has a conversion pattern ROM. The conversion pattern ROM stores conversion patterns each converting the input write address signal block address to a block address for a completely read block area so as to perform simultaneous read and write access even if the data read direction (order) of the frame memory is different from the data write direction. The address converter supplies the write block address to the frame memory. As a result, the data can be written in the completely read block.

Abstract: A column shorted and full array shorted functional plane for simultaneously transferring, or shorting, data to and from the data exchange subsystems of the array processor. This functional plane nominally includes an array of pseudo-modules that architecturally corresponds to the module arrays of the other functional planes of the array processor. Thus, a pseudo-module is present in each of the elemental processors. These pseudo-modules are associated as columns that are each interconnected by a shorted plane column data exchange subsystem. These columns are, in turn, associated with column control logic circuits that each include a column memory register. A mode decode logic circuit establishes the operating configuration of the column control logic circuits.

Abstract: The UNIX.RTM. and $MS-DOS sup R $ operating systems are supported in a multi-tasking computer. At the heart of the computer is a microprocessor having protected and non-protected modes. The computer includes special-purpose hardware which prevents the MS-DOS system and its applications, which execute in the non-protected mode, from interfering with the UNIX system and its applications, which execute in the protected mode. In particular, this hardware monitors addresses generated by the computer and, by selectively inhibiting the associated control pulses, prevents the MS-DOS system from, for example, writing in UNIX-system-allocated memory, or accessing I/O devices that the UNIX system is currently using. In addition, a context switching feature is provided whereby the user can select, via a keyboard operation, to have displayed on the computer video monitor at any given time the image generated from the current UNIX system screen data or the image generated from the current MS-DOS system screen data.

Abstract: A memory (90) comprising a non-volatile memory and a volatile memory, contains a test word and other words which represent a complete user-selected configuration profile. The configuration profile is stored in the memory (90) by a microprocessor (36) automatically when power is interrupted. A second power supply (80) provides operating power to the memory (90) so that the memory (90) can complete its storage cycle even after primary power has failed. The microprocessor (36) checks memory (90) for the test word to verify that the memory (90) has been programmed with a configuration profile and is not missing or defective. The modem (12) resets when power is first applied and when the power supply (75) noise exceeds a predetermined safe level. A concealed jumper strap (61) allows for the reversible placement of the modem (12) into a "dumb" mode wherein the configuration profile cannot be altered.

Abstract: A series of instructions N, N+1, N+2, etc. are issued by an instruction buffer 14 at a fixed clock rate in a pipelined method to parallel instruction flow path 6 and control word flow path 8, each path including a serial coupled holding register 20, 21, an instruction register 18, 19 and a function register 16, 17. If instruction N is a jump instruction, it and the related control word, when stored in the function registers 16, 17 causes the jump target instruction and the related control word of the jump instruction N to be entered into the holding register 20, 21. If the jump instruction N jump conditions are satisfied, the jump target instruction and related control word are written into the instruction registers 18, 19 and then into the function registers 16, 17 to be executed by the associated system.

Abstract: In a processing system (10) comprising a main memory (102) for storing blocks (150) of four contiguous words (160) of information, a cache memory (101) for storing selected ones of the blocks, and a two-word wide bus (110) for transferring words from the main memory to the cache, the cache memory is implemented in two memory parts (301, 302) as a two-way interleaved two-way set-associative memory. One memory part implements odd words of one cache set (0), and even words of the other cache set (1), while the other memory part implements even words of the one cache set and odd words of the other cache set. Storage locations (303) of the memory parts are grouped into at least four levels (204) with each level having a location from each of the memory parts and each of the cache sets. The cache receives a block over the bus in two pairs of contiguous words. The cache memory is updated with both words of a word pair simultaneously.

Abstract: A write protect system prevents inadvertent attempts to write data into a permanent memory storage device (such as a disc drive) containing valuable data that might be destroyed by such a write attempt. The write protect system includes a controller coupled to at least one memory storage device via information transfer busses and a control data bus. The controller sends signals for writing data into selected ones of memory devices. A circuit is coupled into the control data bus for monitoring signals transmitted thereover. Responsive to the monitoring circuit, access is barred to preclude writing into a specific one of the memory devices whereby data may not be accidentally written into the specific memory. The barring is cancelled if a specific action is taken whereby data may be deliberately written into a specific memory.

Abstract: A plurality of external storage devices for storing therein data processing history information. The history information obtained from the processing executed in a data processing system is cyclically written in principle in these external storage devices each time the history information occurs, thereby distributing the load required for the processing to store the history information.

Abstract: A multilingual processor is disclosed herein, for building screen images on the display screen and for decoding multilingual commands, in an information processing system. The information processing system includes an execution unit having a memory, a bulk storage and a workstation connected thereto, the workstation including a keyboard connected to a display screen for inputting command and working text information to the display screen. The multilingual processor includes a document library stored in the bulk storage device including a plurality of language documents and at least one user document. The language documents each characterize a selected language and include a displayable components portion and an executable components portion. A language document selector accesses a selected one of the plurality of language documents in response to a user language selection input from the keyboard specifying that commands and messages are to be in one of the selected languages.

Abstract: Surface fill using Bresenhem algorithm concepts can be adapted to handle the hidden surface and shading functions required in solids modelling. A first plurality of vector generators provides the surface fill function, a second plurality of vector generators provides the hidden surface function, and a third plurality of vector generators provides the shading function. All three pluralities of vector generators can be run in unison to increase the speed at which images of solids can be generated by a factor of 1000.

Abstract: An addressing device for a memory, such as a dynamic memory ROM or RAM, addressable by address words at a predetermined clock-period rate. Each address word is made up of first and second address words composed of least significant and most significant bits of the address word respectively. The first and second address words are multiplexed. The device comprises an adding circuit for incrementing the first address words in terms of a predetermined digital signal carrying words that are synchronous with the first address words and for incrementing the second address word in each address word by unity whenever the first word of the address word has bits all equal to "1", and a shift circuit looped across the adding circuit in order to deliver the first and second multiplexed address words to the memory.

Abstract: A microcomputer memory system is organized into a plurality of banks (16). Each back consists of an array of static column mode dynamic random access memories (DRAMs) of the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from a CPU (10) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the contents of the distributed cache with the contents of the addressed row for that bank.

Abstract: A fast frame store incorporating a memory array having selectable memory banks which include a plurality of relatively slow dynamic RAMs (DRAMs) is disclosed. The frame store has a buffered input and a buffered output to slow the data rate. Data can be read in parallel into a selected memory bank while at the same time other data are being read in parallel out of another selected memory bank. Refresh of DRAMs of an unselected bank occurs simultaneously with the transfer of data to or from the frame store. Several memory banks of the frame store are connected to a single row address select (RAS) line, so that when a selected bank is being addressed for data transfer, the memory location of several other unselected banks are being refreshed.

Abstract: A direct memory access controller, such as for a disk, includes address registers containing beginning and end addresses defining a transfer area of a disk, a location counter which points to a specific location which is being accessed in the transfer area, updating circuitry to set the location counter to the initial address after the location corresponding to the end address has been accessed, and termination circuitry for disabling the location counter when all of the memory locations of the transfer area have been accessed. The address initially loaded into the location counter is for the location which can be accessed most quickly by the direct memory access controller.

Abstract: A Multiple Unit Adapter is disclosed which provides a high speed interface between a single Scientific Processor and a plurality of High Performance Storage Units. This Multiple Unit Adapter is required only when more than one High Performance Storage Unit is used in the data processing system. Since the Scientific Processor of the data processing system is configured with only a single High Performance Storage Unit port its design is simplified and, of course, its cost is reduced. This is especially so when the data processing system uses only a single High Performance Storage Unit. It therefore enables the data processing system to be expanded into a system having a larger memory capacity while keeping the design of the Scientific Processor constant, less complex and consequently less costly.