Abstract: A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement within the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory.The present cache architecture and control features render broadcasting between the data cache and instruction cache unnecessary. Modification of the instruction cache is not permitted. Accordingly, control bits indicating a modification in the cache directory for the instruction cache are not necessary and similarly it is never necessary to store instruction cache lines back into main memory since their modification is not permitted.

Abstract: A dual ported buffer memory for a hierarchical memory, cmprising an addressable memory array for multi-bit words and a multi-bit register. Data is transferred a word at a time between the memory array and a multi-bit bus to a higher level in the memory system and between the memory array and the register. Data is transferred a bit at a time between the register and a single serial line. Concurrent operations are possible for transfers between the memory array and the parallel bus and between the register and the serial line.

Abstract: A microcomputer system has a peripheral storage control equipped with both a circuit which is responsive to a transfer command received from an MPU to set in a counter a transfer start address, which is designated subsequent to that command. The counter to supply an address for a buffer to control transfer of data from the output of the buffer to a common bus connected between the MPU and a RAM. A circuit is provided for controlling the aforementioned counter to count up in response to a transfer acknowledge signal which is subsequently received from a direct memory access control.

Abstract: A system and method for inputting data to a single port of a host computer in parallel from a terminal keyboard and a graphic data digitizer. An adapter circuit includes inputs from the digitizer, the host computer and the terminal, outputs to the host computer and terminal and switching circuitry for routing signals from selected inputs to selected outputs, so that the use of the digitizer is transparent to the host computer. A microprocessor in the adapter circuit controls switching and, additionally, is programmed so that the digitizer, provided with menu images of keyboards, can mimic the function of the keyboard. The microprocessor memory contains a coordinates map of the menus, locatable as the user desires in the work area, which allows the user to access stored keyboard symbols and functions by using the digitizer.

Abstract: A microprocessor memory safeguard device comprising a switch having two it terminals and a common terminal. The common terminal is connected to a first terminal of the memory and to the logic zero of the microprocessor. The other input terminal of the switch is connected to one terminal of a battery. The second terminal of the memory is connected to the other terminal of the battery. The second input terminal of the switch is connected to an initialization line of the processor whose initialization input is also connected to the line. The initialization line is connected directly to a power supply source. The initialization line could also be a data bus interconnecting a plurality of microprocessors.

Abstract: A data processing system that can execute a plurality of programs concurrently and has a display screen for displaying data associated with any one of the programs. Each program maintains display screen data indicating the current status of the program. The system maintains a REVIEW menu containing a list of the programs that have display screen data available. When a REVIEW key is pressed, the REVIEW menu is displayed. By pressing a further key, one of the listed programs can then be selected, and its display screen data is displayed on the screen. When the key is released, the information that was being displayed prior to operation of the REVIEW key is restored to the screen. A RESUME menu lists programs that are currently in a background mode, and can be called up by pressing a RESUME key, allowing one of those programs to be put into a foreground mode in which it has access to the screen.

Abstract: An access control system for controlling the access to a storage which is divided into a hardware area inaccessible to ordinary programs and a software area for storing the ordinary programs, includes an address registration device and access controller. The address registration device has a plurality of entries, each of which holds a previously-used address of the storage and a flag for indicating whether the previously-used address is included in the hardware area or not. Further, the address registration device indicates whether an address at which the storage is to be accessed, is present in the address registration device or not. The access controller controls the access to the storage in accordance with the flag from the address registration device, a signal indicative of whether the to-be-accessed address of the storage is present in the address registration device or not, and the access mode which is now used.

Abstract: In a multiprocessor system comprising a plurality of processor units (11 and 12) which are loosely coupled to one another and which individually carry out processing operations in accordance with control signal sets, respectively, a common memory (15) comprises subareas (33.sub.1 and 33.sub.2) assigned to the processor units and loaded with the control signal sets. Each control signal set is written into each subarea from each main memory (22) included in each processor unit whenever each control signal set is renewed. When a particular one of the processor units falls into disorder and interrupts the processing operation, another of the processor units accesses the subarea assigned to the particular processor unit and loads its main memory with the control signal set of the particular processor unit. Another processor unit thus takes over the processing operation interrupted by the particular processor unit.

Abstract: A data processor control unit which provides instructions for execution by a data processor and minimizes instruction cycles lost as overhead. A pipelined instruction stream is used in which instruction addresses are selectively coupled from a program counter and a prefetch counter to a program memory which provides actual instructions. The instructions are stored in a prefetched register, decoded and then loaded into an instruction register coupled to the data processor. When an interrupt service request is made by a device peripheral to the processor, the prefetch instruction address flow is immediately redirected and a predetermined number of interrupt instruction words are prefetched by an interrupt address generator before completion of execution of normal program instructions has occurred. Therefore, interrupt instructions are fetched and jammed into a pipelined instruction stream regardless of instruction cycle boundaries.

Abstract: A new method of refreshing a dynamic RAM, uses relatively simple circuitry. Refreshing of the dynamic RAM can be implemented while smoothly accessing any a real-time based high-speed devices such as a floppy disc driver.In a microprocessor system comprising a central processing unit (CPU), a dynamic RAM, and a plurality of input/output ports, a refreshing process of the dynamic RAM can occur in one of two modes. When input/output (I/O) accesses are not being performed by the CPU, a burst mode refreshing process takes place. However, when input/output (I/O) accesses are to be performed, a refreshing process of the dynamic RAM can be implemented within a period while the CPU accesses the input/output (I/O) port addresses.

Abstract: A memory for use in a digital data processing system, the memory including a memory controller and one or more memory arrays. A memory array performs refresh operations transparently to the memory controller, but in synchronization with a system timing signal while it is receiving normal system power. A memory array also includes asynchronous refresh circuitry for controlling refresh while the system power is interrupted and the array receives no system timing signal. When each refresh operation occurs during power interruption, the asynchronous refresh circuitry tests the condition of the system power supply. Since refresh operations are transparent to the memory controller, the memory array indicates when the memory operations are completed. If the memory operation is a read operation, the memory controller then controls the transfer of data from the array to the controller.

Abstract: This circuitry expands the memory addressing arrange of a microprocessor beyond its directly addressable memory capacity. This circuit uses the status outputs of the microprocessor to segregate memory accesses for program code instructions from accesses for other data. This segregation scheme assigns different memory banks to program code instructions and to data. Memory reads and writes for scratch pad data are performed from one bank of memory. Memory reads for program code instructions are performed from a separate memory bank. This memory bank technique can double the size of a microprocessor's directly addressable memory without changing the microprocessor's architecture. This circuitry is suitable for implementation with CMOS gate array technology.

Abstract: An elastic buffer includes a memory array for storing received data, each location within the array having an associated cell storing a flag indicative of the most-recently performed (i.e., read or write) on the associated memory location. A potential write overflow of the memory is detected whenever a write attampt is made to a location whose flag indicates a write was most-recently performed. A potential read underflow is detected whenever a read attempt is made to a location when the flag associated with the location next to be read indicates a read was most recently performed. Also, a potential write operation of a memory location prior to the completion of a read on the next location within the array are also generates an overflow/underflow condition. Metastable logic state conditions within the array are avoided because the potential overflow/underflow conditions take cognizance of the finite propogation and setting times of signals within the array.

Abstract: A high speed data transfer method and apparatus. A high speed data bus includes separate data transfer and master control bus portions. A system host computer loads a sequence of source and destination addresses corresponding to communications units coupled to the bus into memory in a bus master controller. The bus controller sequences through these address pairs at an aggregate rate greater than at least some of the devices' ability to transfer data to enhance data transmission speed on the bus. Bus cycles are allocated to devices on the bus according to a scheme dependent on those devices ability to utilize the bus. High speed devices are allocated a greater number of bus cycles per unit time than slower devices.

Abstract: In a storage control apparatus only vector elements indicated as write data by a corresponding mask information among the vector elements stored in a storage device are stored to the pertinent memory locations of a desired vector register in the vector processor based on the mask information which indicates whether or not the write operation is required (for example, "1" indicates that the write operation is necessary and "0" indicates that the write operation is unnecessary). When the mask information indicates that the write operation is not required, the storage control apparatus controls operations to prevent the memory bank of the main storage from being set to the busy state, thereby eliminating the memory bank conflict which should not take place in accordance with the intrinsic system characteristics.

Abstract: A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memory wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page Table or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address.

Abstract: The invention disclosed and claimed herein provides a method for a virtual machine, which maps to the V=R region of a host machine's address space, to resume program execution successfully when the host operating system terminates and subsequently restarts successfully after the occurrence of a system incident. The system incident brings the computer system down, but with a reasonable chance that the system will be able to bounce. A bounce occurs when the host operating system nucleus is reinitialized or refreshed. The virtual machine will be allowed to survive the system incident as long as its integrity can be maintained, i.e. as long as its status and in-progress work can be preserved.

Abstract: There is provided a method of dynamically changing the formation of addresses in a memory of a data processing system having a segment descriptor register adapted to hold segment descriptor words for prescribing segments containing instruction words and data stored in the memory and having memory addresses, an address register for designating addresses of the data, and an instruction counter for designating addresses of the instruction words.

Abstract: The microprocessor unit of a system implemented using metal-oxide-silicon (MOS) technology, is driven by a variable-frequency clock. The microprocessor controls the clock frequency based on the present rate of required microprocessor activity. By driving the microprocessor unit at a lower clock frequency when such activity rate is low, the energy dissipated by the microprocessor unit is reduced due to the MOS power-frequency characteristic.

Abstract: A method and apparatus for transferring data between two data processors includes transferring a data byte from the first processor to a latch member, setting a flip-flop circuit which generates an interrupt signal to the second processor enabling the second processor to transfer the data byte from the latch member to a RAM memory unit associated with the second processor. The second processor resets the flip-flop circuit which outputs a signal to the first processor enabling the first processor to transfer another data byte to the latch member. Steering address bits associated with each of the processors are used to provide control signals to select the storage member in which the data bytes are to be transferred. A second flip-flop circuit associated with the second processor allows the second processor to transfer data to the first processor in the same manner.