Abstract: A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor.

Abstract: A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors.

Abstract: A content searching chip and system based on a peripheral component interconnect (PCI) bus. The content searching chip includes a peripheral component interconnect interface module, a protocol conversion module, and a content storage module. The content storage module is connected to the protocol conversion module using an instruction bus and a data bus.

Abstract: A method for detecting a receiver on a computer bus, comprises the steps of: applying a low voltage state on transmission lines of the computer bus using a voltage mode driver; applying a high voltage state on the transmission lines using the voltage mode driver; determining a voltage rate change for transmission voltages on the transmission lines; and determining the presence of the receiver on the computer bus as a function of the voltage rate change.

Abstract: A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases.

Abstract: A method and system for controlling power is provided. The system is configured to selectively control a plurality of power control domains. The system may be configured to process audio data in at least one of the domains. The system may be configured to output audio data, while one or more of the power control domains is suspended.

Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

Abstract: A computing device to couple with a second computing device. The computing device switches between a master mode and a slave mode based on whether the computing device is docked with the second computing device.

Abstract: Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.

Abstract: A docking assembly for docking a handheld device thereto is provided. The docking assembly includes a cradle for receiving the handheld device, and a handle adjacent to the cradle and reciprocally movable inwardly and outwardly relative to the cradle between an open and a position. The handle has a handle interface facing a corresponding device interface of the handheld device when the handheld device is placed in the cradle. The handle interface has a pair of alignment projections and a handle data connector connectable to a device data connector of the handheld device, the alignment projections being engageable with complimentary alignment cavities of the handheld device. The docking assembly further includes a displacement mechanism configured such that, as the handle moves toward the closed position, the alignment projections progressively engage the alignment cavities and guide the handle and device data connectors toward each other for connection therebetween.

Abstract: A method of performing collective communication in a collective communication system includes processing nodes, including: determining whether a command message, regarding one function among a broadcast function, a scatter function, and a gather function, is generated by a processor; determining a transmission order between the processing nodes by giving transmission priorities to processing nodes that do not communicate, based on a status of each of the processing nodes if it is determined that the command message regarding the one function among the broadcast function, the scatter function, and the gather function, is generated by the processor; and performing communication with respect to the command message based on the determined transmission order.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract: Exemplary embodiments of methods and apparatuses to manage a power of a system that leverage intermediate power margins are described. One or more subsystems of the system are operated at one or more performance points. A power consumed by the one or more subsystems at each of the one or more performance points is measured. An operational power of the one or more subsystems at the one or more performance points is determined. The one or more subsystems are operated at well-known conditions at the one or more performance points. The operational power may be adjusted based on data associated with the one or more subsystems. The operational power is provided to a power lookup table. The power is distributed among the one or more subsystems based on the operational power.

Abstract: A system and method for providing a docking station that supports bi-directional high speed data, high bandwidth display, and power to a computing device utilizing a standard connector on the computing device are described. This includes a standard connector on the computing device including a standard digital display connector having a first set of two lanes and a second set of two lanes, a USB host that provides USB signals that enable bi-directional high speed data, a digital display source that provides digital display signals that enable high bandwidth display and couples digital display signals to the digital display connector on the second set of lanes, a multiplexor that receives signals from the USB host, receives signals from the digital display source, and couples the USB signals to the digital display connector on the first set of lanes, and a power subsystem that receives power via the digital display connector.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: An interface device for exchanging data between a first bus system and a second bus system, wherein an input/output device is connectable to the second bus system and within the input/output device includes an addressable slot and an addressable subslot for output or acceptance of input/output data to optimize the consistent exchange of the data between the bus systems. A data transfer device including a transfer memory is connected via the control device and a list storage device in which a data structure for addressing the data for the input/output device is stored, and wherein the data structure is predetermined for a plurality of subslots in a telegram format of the telegrams of the first bus system.

Abstract: A system for the management of rack-mounted field replaceable units (FRUs) that affords the enhanced availability and serviceability of FRUs provided by blade-based systems but in a manner that accommodates different types of FRUs (e.g., in relation to form factors, functionality, power and cooling requirements, and/or the like) installed within a rack or cabinet.

Abstract: A system for the management of rack-mounted field replaceable units (FRUs) that affords the enhanced availability and serviceability of FRUs provided by blade-based systems but in a manner that accommodates different types of FRUs (e.g., in relation to form factors, functionality, power and cooling requirements, and/or the like) installed within a rack or cabinet.

Abstract: A system for the management of rack-mounted field replaceable units (FRUs) that affords the enhanced availability and serviceability of FRUs provided by blade-based systems but in a manner that accommodates different types of FRUs (e.g., in relation to form factors, functionality, power and cooling requirements, and/or the like) installed within a rack or cabinet.

Abstract: Integrated circuits with memory elements are provided. Data may be loaded into the memory elements using write driver circuitry. The write driver circuitry may be provided with a fixed positive power supply voltage and an time-varying ground power supply voltage that is less than the positive power supply voltage. The time-varying ground power supply voltage may be generated using programmable power supply circuitry. The programmable power supply circuitry may include a pulse generation circuit and a configurable capacitive circuit. The pulse generation circuit may output a pulse signal to the capacitive circuit. In response to receiving the pulse signal, the capacitive circuit may push the time-varying ground power supply voltage to a negative value. The time-varying ground power supply voltage may be driven below zero volts for at least a portion of a write cycle to help improve write margins and increase memory yield.