Abstract: A computer system and a method are provided for accessing a peripheral component interconnect express (PCIe) endpoint device. The computer system includes a processor, a PCIe bus, and an access proxy. The access proxy connects to the processor and the PCIe endpoint device; the processor acquires an operation instruction, where the operation instruction instructs the processor to access the PCIe endpoint device through the access proxy, and send an access request to the access proxy according to the operation instruction; and the access proxy sends a response message of the access request to the processor after receiving the access request sent by the processor. Because the processor does not directly access the PCIe endpoint device to be accessed but completes access through the access proxy, thereby avoiding a machine check exception (MCE) reset for the processor.

Abstract: A chained information exchange system (10) comprising a chain of modules (1, 2, 3, 4, 5), each module (1, 2, 3, 4, 5) being connected to one or two other modules (1, 2, 3, 4, 5) via digital buses (11, 12, 13, 14, 15), thereby forming a chain that is open or else a continuous loop that is closed. Each digital bus (11, 12, 13, 14, 15) is a hardened digital bus, capable of withstanding external electromagnetic disturbances, and it is unidirectional. A signal travels in said information exchange system (10) and consequently through each module (1, 2, 3, 4, 5), and after passing through a module (1, 2, 3, 4, 5), said signal contains information that the module (1, 2, 3, 4, 5) through which it has passed does not modify and that is addressed to at least one other module (1, 2, 3, 4, 5), together with specific information that has been added by said module (1, 2, 3, 4, 5) through which it has passed and that is addressed to at least one other module (1, 2, 3, 4, 5).

Abstract: An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a clock signal and creates data transmission link to the computer device. The master storage unit has a master clock pin, at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has a slave clock pin and at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, such that the command signal from the microprocessor is sent from the master storage unit to the slave storage unit via the relay bus.

Abstract: An enhanced serial interface system is disclosed. The system includes a master component and a slave component. The master component is configured to operate in a standard mode and an enhanced mode for communication. The master component includes standard terminals and hybrid terminals. Only the standard terminals are used for communicating in the standard mode. The hybrid terminals and the standard terminals are used for communicating in the enhanced mode. The slave component is configured to operate in the enhanced mode and communicate with the master component.

Abstract: Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Abstract: According to some embodiments, a method and apparatus are provided to receive a first data burst associated with a first data line and a second data burst associated with a second data line, determine a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst, and output data comprising the first data burst and the first one or more stuff bits and the second data burst and the second one or more stuff bits.

Abstract: The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction.

Abstract: A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and connecting by a set of busses formed according to a set of design rules specifying tracks having a minimum size of conductors and a minimum spacing between conductors. The busses are routed in a preferred direction. The busses include minimum size conductors at alternate tracks within a selected metal layer of the semiconductor and minimum size conductors at alternate tracks in a different metal layer. The conductors in the different metal layer are connected to corresponding connectors in the selected metal layer by vias. Shields of conductors not connected to the bus may be included in tracks not including bus conductors.

Abstract: A receiver circuit configured to operate in a DisplayPort (DP) mode and a High-Definition Multimedia Interface (HDMI) mode. The receiver circuit includes: termination circuitry configured to receive a DP signal in the DP mode and an HDMI signal in the HDMI mode; and voltage common-mode (VCM) level shifter circuitry configured to operate as a pass-through for the DP signal in the DP mode and generate a converted HDMI signal from the HDMI signal in the HDMI mode.

Abstract: A disclosed computer system includes a processor, an I/O hub including a first host bus interface to communicate via a first transport bus, and a sensor hub. The sensor hub includes a first transport bus interface and a sensor hub microcontroller. The sensor hub microcontroller includes a peripheral stack that includes a second transport bus driver to communicate with a peripheral device via a second transport bus. The peripheral device may comply with a device specification such as the human interface device (HID) standard. The peripheral stack further includes a second transport bus plugin to adapt bus-specific operations to generic operations for the device specification, a device class driver to communicate bus-independent peripheral reports based on the generic operations, and a peripheral management module to coalesce multiple peripheral reports into a single instance visible to the I/O hub via the first transport bus interface and the first host bus interface.

Abstract: Embodiments of the present invention relate to electronic devices and data transmission methods. The electronic device includes: a first part including a first main board, a first processor connected to the first main board, at least one sharable hardware component and a first connector; and a second part including a second main board, a second processor connected to the second main board and a second connector corresponding to the first connector. The first part and the second part are connectable to each other via the first connector and the second connector. The first connector is configured to receive, from a first driving module of the hardware component, a first data sent from the hardware component via a first connector driving module, and transmit the first data to the second connector such that a second connector driving module can provide the first data from the second connector to a first application running in the second part via a second driving module of the hardware component.

Abstract: A method for setting a working mode of a multi-processor system includes: detecting, after a current board is inserted into a slot of the backplane, whether an associated board exists on the backplane; detecting, if the associated board exists, whether the associated board is in an independent working state; powering on the current board according to a slave working mode if the associated board is not in an independent working state, so as to work coordinately with the associated board; detecting, within a predetermined detection time if the associated board does not exist, whether a board is inserted into another slot of the backplane except the slot of the master board; and powering on the current board according to a master working mode if it is detected that the board is inserted, so as to work coordinately with the board in the other slot.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: A processing unit exchanges data with another processing unit across a data connector that supports a particular communication protocol. When the communication protocol is updated to support a new packet type, a specification of that new packet type may be stored within software registers included within the processing unit. Under circumstances that require the use of the new packet type, packet generation logic may read the packet specification of the new packet type, then generate and transmit a packet of the new type.

Abstract: A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed.

Abstract: A system and method of scheduling tasks, comprising receiving activity and performance data from registers or storage locations maintained by hardware and an operating system; storing calibration coefficients associated with the activity and performance data; computing an energy dissipation rate based on at least the activity and performance data; and scheduling tasks under the operating system based on the computed energy dissipation rate.

Abstract: An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt priority unique to a device, and manages an interrupt number priority conversion table showing the relation between the interrupt number and the interrupt priority. Each device continuously outputs an interrupt request having the same interrupt number until the interrupt processing is completed. An interrupt controller converts the interrupt number into the interrupt priority in accordance with the interrupt number priority conversion table when there is an interrupt signal from the devices.

Abstract: In accordance with one or more example aspects of the disclosure, communications are effected on a bus using bit time and slew rate feedback. As consistent with one or more embodiments, communications are effected in a network including a master circuit and a plurality of slave circuits, on bus that is controlled by the master circuit corresponding to master and slave data communication. A feedback signal is provided, which is indicative of a slew rate and bit time of signals communicated between the master and slave circuits on the bus. Data is transmitted on the bus by generating output signals via a waveform corresponding to an input signal, and controlling the waveform based upon the slew rate and bit time indicated via the feedback signal.

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Abstract: The use of asset connectivity verification and switchable asset connectivity activation techniques may reduce or eliminate occurrences of human errors with respect to the improper connection and activation of infrastructure components in a data center. Assert connectivity verification involves the acquisition of identifiers corresponding to infrastructure component interfaces that are coupled to each other, and comparing the identifiers to pairing specifications to verify that the coupling of the infrastructure components comply with pairing specifications. Asset connectivity activation involves determining whether the coupling of a switchable coupler to one or more component interfaces complies with pairing specifications based on the corresponding identifiers of each component, and activating the switchable coupler to enable the flow of data signals and/or power when the coupling of the components meets the pairing specifications.