Abstract: A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. The microprocessor can access the auxilary chip to ascertain the power history. That is, the microprocessor can direct an interrupt to the auxilary chip, which will cause the auxiliary chip to respond with a signal which indicates to the microprocessor whether the power supply voltage is heading up or down. When the microprocessor is reset at power-up, the present invention permits the microprocessor to determine (by querying the auxiliary chip) whether the supply voltage is marginal, so that the microprocessor does not go into full operation until the supply voltage is high enough.

Abstract: In a cache controller having a cache disposed between a CPU and a direct access storage for temporarily storing therein data transferred between the CPU and the storage, data is written from the cache into the storage in a write after mode. There is employed an update generation identifier specified by the CPU at each predetermined point of time. When storing data (write after data) from the cache into the storage in the write after mode, the last update generation specified prior to when the data is first written in the cache is set as the update generation of the data. When an update generation is specified by the CPU, write after data having a generation older than the specified generation by a predetermined effective management generation number n or more is preferentially written in the storage.

Abstract: A structure and a method provide data integrity for a multiprocessor system having a cache memory and a snoop tag cache. In one embodiment, the snoop tag cache copies the tags of a primary cache. Whenever a write operation occurs, the snoop tag cache is accessed to determine if the accessed tag matches a predetermined portion of the address of the memory location on which the write operation is performed. If so, a signal is sent to the CPU associated with the primary cache so that the corresponding entries in the primary cache and the snoop tag cache can be invalidated.

Abstract: A cache control circuit reduces the number of accesses to main memory in a multiprocessing system. The circuit allows a cache memory associated with one Central Processing Unit (CPU) to recognize and respond to memory requests from another CPU, and includes specialized circuitry to support burst-mode operations. Data in one cache memory may be transferred to another cache without the need to access main memory. The direct transfer of requested data between caches in a multiprocessor system results in providing the requested data quickly and also reduces the traffic in the memory bus. By transaction duration can further be reduced by making the snooping cache smarter.

Abstract: A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time.

Abstract: A method for reliably storing management data in a flash EEPROM memory array, which array is divided into a plurality of individually-erasable blocks of memory cells and in which each of the blocks of memory cells has stored thereon data regarding management of the array during a cleanup process in which valid data stored in a first block is written to another block of the array, and then the first block is erased. The process includes the steps of storing data regarding management of the array from the first block in random access memory and, in an enhanced process, on another block before erasure of the first block. The data may then be rewritten to the first block after the erase.

Abstract: The cache keeps regularly accessed disk I/O data within RAM that forms part of a computer systems main memory. The cache operates across a network of computers systems, maintaining cache coherency for the disk I/O devices that are shared by the multiple computer systems within that network. Read access for disk I/O data that is contained within the RAM is returned much faster than would occur if the disk I/O device was accessed directly. The data is held in one of three areas of the RAM for the cache, dependent on the size of the I/O access. The total RAM containing the three areas for the cache does not occupy a fixed amount of a computers main memory. The RAM for the cache grows to contain more disk I/O data on demand and shrinks when more of the main memory is required by the computer system for other uses.

Abstract: A DRAM control circuit according to the present invention, comprising a DRAM, a DRAM controller adapted for receiving an address, write data, and a data rewrite command from a host controller and designating a row address and a column address to the DRAM, and a column address strobe signal control circuit, causes pseudo column address strobe signal DCASq-N to have "L" level to read the contents of the address when column address strobe signal DCAS-N and read signal RD-N have "L" level, causes pseudo column address strobe signal DCASq-N to have "H" level to set an input/output terminal I/O to high impedance when the read signal RD-N has "H" level, further causes pseudo write signal WR-q to have "L" level to output write data to a data bus when the input/output terminal I/O remains at the high impedance, and rewrites the contents of the address to the write data when the pseudo column address strobe signal DCASq-N is caused to have "L" level.

Abstract: A early bus grant prediction technique combines the operating advantages of both a split transaction bus and a simple shared bus. When a read request is generated by a memory access requester, an early bus request is generated for the impending data transfer. The early bus request is provided to bus grant prediction and arbitration logic that determines whether or not the bus will be available at the time the requested data has been retrieved and is ready for transfer. If the bus is available, the retrieved data is routed immediately to the memory bus for a fly-by transfer. On the other hand, if the bus is not available, the data is routed to a FIFO buffer to be transferred when the bus is available.

Abstract: The present invention is an improved method and apparatus for selecting and replacing a block of a set of cache memory. The present invention provides for the weighted random replacement of blocks of cache memory by assigning indices to the memory blocks of a given set of cache memory. One of the assigned indices is then randomly selected by the present invention. The memory block of the given set to which the randomly selected index is assigned is replaced. The indices are assigned such that one or more blocks of the given set of cache memory have a high probability of replacement, whereas the other blocks of the given set of cache memory have significantly lower probabilities of replacement.

Abstract: To provide a boundaryless burst mode access, a memory array is divided into two or more subarrays. Each subarray has its own row and column decoders. The columns of each subarray are divided into groups. A sense amplifier circuit is provided for each group of columns. The column decoder of each subarray selects simultaneously one column from each group so that the memory locations in one row in the selected columns have consecutive addresses. The memory locations in the selected row and columns are read by the sense amplifier circuits. While the contents of the sense amplifier circuits of one subarray are transferred one by one to the memory output, consecutive memory locations of another subarray are read to the sense amplifier circuits. In some embodiments, to save power, sense amplifier circuits are disabled when their outputs are not transferred to the memory output.

Abstract: A method and device for avoiding unnecessary data broadcasts by detecting the presence of additional cache-equipped bus-masters is provided. The device includes a master bus-master equipped with a local cache arrangement for caching data originating in a system memory. The master bus-master communicates with the system memory over a bus, and is coupled to a control line at an input. Any cache-equipped slave bus masters that are caching data with the system memory are coupled to the control line by an output and are configured to generate a signal at the output to drive the control line to a predetermined state to indicate that they are caching data. The master bus-master detects the state of the control line and determines whether the data being buffered in its local cache arrangement is shared based upon the state of the control line.

Abstract: A controller for a disk array with parity and sparing includes a non-volatile cache memory and optimizes the destaging process for blocks from the cache memory to both maximize the cache hit ratio and minimize disk utilization. The invention provides a method for organizing the disk array into segments and dividing the cache memory into groups in order of least recently used memory locations and then determining metrics that permit the disk array controller to identify the cache memory locations having the most dirty blocks by segment and group and to identify the utilization rates of the disks. These characteristics are considered to determine when, what, and how to destage. For example, in terms of maximizing the cache hit ratio, when the percentage of dirty blocks in a particular group of the cache memory locations reaches a predetermined level, destaging is begun. The destaging operation continues until the percentage of dirty blocks decreases to a predetermined level.

Abstract: A cache system which includes prefetch pointer fields for identifying lines of memory to prefetch thereby minimizing the occurrence of cache misses. This cache structure and method for implementing the same takes advantage of the previous execution history of the processor and the locality of reference exhibited by the requested addresses. In particular, each cache line contains a prefetch pointer field which contains a pointer to a line in memory to be prefetched and placed in the cache. By prefetching specified lines of data with temporal locality to the lines of data containing the prefetch pointers the number of cache misses is minimized.

Abstract: Disclosed is a solid state disk drive, including a volatile, electronic RAM, memory and a non volatile, magnetic disk. The drive continuously saves unique data stored in the memory back to the disk. Additionally, the drive includes a number of tables and bit fields, in both volatile electronic memory and disk, for generally keeping track of what data has been restored from disk to memory, what data in the memory has been modified since it was restored from disk, and what modified data in the memory has been saved back to disk. In the event of a primary power outage, the drive first saves the volatile tables onto disk, and then saves the volatile, modified data onto disk, while using auxiliary power. If, however, auxiliary power is lost before any or all of the modified data is saved on disk, the saved tables provide information which enables the drive to distinguish the valid from the invalid data on disk.

Abstract: A method and system for caching graphic information for display in a graphics processing system to avoid repeated rendering each time a graphic is required to be re drawn. A developer of an application program can specify which graphic objects should be cached, and request that caching be carried out for those graphics. Devices may also specify whether caching is desired, and this preference may be overridden by the caching system. The caching system may create a single cache object for several devices, or may create several cache objects for corresponding devices, depending on the characteristics of the devices. The objects are cached in a device-dependent manner. The cached graphic may be sent to methods and devices in the same mariner that any other graphic is sent.

Abstract: A system and method for managing caches in a multiprocessor having multiple levels of caches. An inclusion architecture and procedure are defined through which the L2 caches shield the L1 caches from extraneous communication at the L2, such as main memory and I/O read/write operations. Essential inclusion eliminates special communication from the L1 cache to the L2, yet maintains adequate knowledge at the L2, regarding the contents of the L1, to minimize L1 invalidations. Processor performance is improved by the reduced communication and the decreased number of invalidations. The processors and L1 caches practice a store-in policy. The L2 cache uses inclusion bits to designate by cache line a relationship between the line of data in the L2 cache and the corresponding lines as they exist in the associated L1 caches. Communication and invalidations are reduced through a selective setting/resetting of the inclusion bits and related L2 interrogation practice.

Abstract: Methods and apparatus are provided for interleaving memory transactions into an arbitrary number of memory banks that need not be equal size. A memory address range is divided into subranges of contiguous addresses. A first embodiment associates the subranges to a unique set of banks. Memory transactions falling within a subrange are interleaved among banks associated with the subrange. A second embodiment associates a set of banks with each subrange. The set of banks of one subrange are not necessarily independent of the set of banks of a second subrange. A third embodiment is a hybrid of the first and second embodiment. Range detection mechanisms are provided for detecting if a memory transaction falls within a subrange. In addition, an ID number is produced from the memory address according to an interleaving algorithm. The ID number is compared to bank ID numbers associated with each of the banks.

Abstract: A disk array system having a plurality of disk units includes an upper-level data transfer controller for controlling transfer of data to and from an upper-level apparatus, a data buffer for temporarily storing therein data from the upper-level apparatus, a drive data transfer controller for controlling the data transfer between the buffer and the units, and a main microprocessor for controlling the the transfer controllers. When transferring data, the microprocessor indicates an address to be used in the buffer and a distribution mode of data to the data transfer controllers so that the data transfer is conducted thereafter without intervention of the microprocessor. During the transfer, the microprocessor can generate information for a subsequent data transfer to indicate the information to the transfer controllers. After a data transfer is terminated, the pertinent transfer controller can immediately execute the next data transfer, which increases the utilization efficiency of the data bus.

Abstract: A communication system which makes possible a very fast data exchange between connected stored program controls, which is important especially for the control of industrial processes. A total storage area is subdivided into partial storage areas, which are assigned to the stored program controls. Only in the start-up phase of a stored program control are complete data words transmitted, whereas during operation only data which has changed is transmitted.