Abstract: A programmable memory controller generates address and control signal information associated with a word of data which is desired to be transferred first from dynamic random access memory (DRAM) modules. The generated information specifically assists memory support circuitry interfacing with page mode DRAMs. This information is normally provided to the memory support circuitry just before selection of the staring word from a fetch line data buffer. Memory latency, gaps in data transfer, can be reduced when this information is available to the support circuitry as it drives column address and/or column address strobe (CAS) signals to the DRAMs.

Abstract: A processor for use in a digital data processing system includes a data path which is controlled by microinstructions from the processor's control circuits. The data path includes a plurality of registers and an arithmetic and logic unit. The source data processed by the arithmetic and logic unit is obtained from the registers and elsewhere in the system as identified by selected fields of the microinstruction, and the processed data is stored in destinations also identified by the source selection fields or other locations. The destination selection field of the microinstruction selects a source identification or another destination as the selected destination.

Abstract: A cache subsystem for a computer system which includes a cache memory and a cache control means. When the processor subsystem of the computer system requests data, information related to the location of the data within the memory subsystem of the computer is input to the cache subsystem. The control means receives an address bus bit field and transmits control signals which vary depending on the received address bus bit field to the cache memory to look for the requested data. The address bus bit field is configured based upon the dimensions of the cache memory and includes information as to where the data would be stored within the cache memory. As different cache memories are of different dimensions, means for modifying the address bus bit field generated by the cache control means based on the dimensions of the cache memory are provided so that the cache subsystem may be readily configured to operate with different sized cache memories.

Abstract: A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

Abstract: A data processing apparatus which allows a large number of micro instructions to be read at high speeds by storing frequently used micro instructions in the on-chip ROM and those less frequently used in the off-chip memory. From the address of the micro instruction to be accessed, it is determined whether the micro instruction is stored in the on-chip ROM or the off-chip memory, and the micro instruction is accessed on the basis of this determination. A cache memory may also be provided on the chip for providing high speed repeat access to micro instructions stored in the off-chip memory.

Abstract: A method and apparatus for routing processor-memory data traffic in a shared-memory multiprocessor computer system employs an interconnection network including two buffered multistage switching networks. Each of these networks can be used to route the data from any processing element to any memory element. Depending on the nature of the processor-memory traffic, two distinct routing schemes are used to distribute the traffic among the two networks. The first method distributes the memory accesses evenly among the two networks and maximizes performance when the memory accesses are uniformly distributed among the memory modules. However, when the traffic is highly non-uniform, a second routing method is used to confine the non-uniform part of the traffic to one network and the remaining part to the other network. The routing method is selected based on the prevailing traffic conditions. A distributed feedback mechanism detects the change in traffic conditions and changes the routing method accordingly.

Abstract: Multiprocessor system having distributed shared resources and dynamical and selective global data replication in which a plurality of processors communicate each with the other through a sytem bus. Each CPU is provided with a local memory storing data used locally and global data shareable by a plurality of processes operative in differing CPUs and therefore replicated in the local memory of each CPU. The global data replication is performed, at page level, only when a global data page is effectively needed by a plurality of processes operative in differing CPUs and in those CPUs where the page is needed, the replication in the other CPUs being performed in a predetermined trash page of the local memory so that memory space required for replication is minimized, as is traffic on the system bus for global data replication and global data writes required for assuring global data consistency.

Abstract: A sequencer including input structure for receiving and retaining sequential data which includes the sequence starting address, the number of blocks in the sequence, the number of words in a block, increment between blocks and increment between words, includes an adder connected between the input structure and an output device and includes a controller for selectively providing to the adders inputs one or more of the sequence starting address, increment between words, increment between blocks and the output of the output device as a function of the number of blocks in the sequence and the number of words in a block.

Abstract: A translation look-aside buffer with a variable page size per entry is disclosed. Each entry can have a different number of bits translated from a virtual address to a physical address. Each entry in the TLB contains an indication of the page size for that entry. When the translation is done, the indication of page size determines how many bits are translated.

Abstract: A text editing apparatus searches a desired character string from a group of stored characters and stores a word within a predetermined range which includes the desired character string into an input character memory.

Abstract: A method of maintaining the consistency of cached data in a client-server database system. Three new locks--a cache lock, a pending lock and an out-of-date lock--are added to a two-lock concurrency control system. A new long-running envelope transaction holds a cache lock on each object cached by a given client. A working transaction of the client works only with the cached object until commit time. If a second client's working transaction acquires an "X" lock on the object the cache lock is changed to a pending lock; if the transaction thereafter commits the pending lock is changed to an out-of-date lock. If the first client's working transaction thereafter attempts to commit, it waits for a pending lock to change; it aborts if it encounters an out-of-date lock; and otherwise it commits.

Abstract: A high speed dual-port burst access memory (BAM) is disclosed that is capable of operating in both a burst access mode and random access mode simultaneously. The architecture of the high speed BAM permits random or burst access read or write operations on one port while simultaneously supporting sequential reading or writing in a burst or random mode of operation on a second port. Burst access can also be stopped and restarted for any number of clock cycles independently at each port. The BAM can also be configured as a high speed FIFO.

Abstract: A method and apparatus for providing memory system status signals in an information processing system is disclosed. The memory system includes a bus which couples a memory unit, for storing information units, to a memory control unit. The memory control unit provides addresses to the memory unit. The memory unit stores or retrieves information units from memory locations corresponding to the provided address. The memory unit provides a status signal to the memory control unit indicating a status of the memory access being provided. The status signals provided by the memory unit indicate whether the provided memory address is within the range of addresses stored in the memory unit, the access speed of the memory devices in the memory unit, or the type of memory devices in the memory unit.

Abstract: A method for transitioning an Intel processor from virtual 8086 (V86) mode to protected mode operation which detects when a virtual V86 processor attempts to transition to protected mode, stores all of the information concerning the virtual processor at the time of the attempt to transition to protected mode, remaps the memory allotted to the virtual processor to the memory space used in running a process in real mode, sets up a dummy stack to provide for operation during a transition to protected mode, moves a process for transitioning to real memory space, shifts all of the register values to values for real memory space, and finally reactivates the transition to protected mode.

Abstract: A digital data processing system includes a plurality of central processor units which share and access a common memory through a memory management element. The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all central processing units requesting access to a given datum residing in memory are signalled of the datum's existence. In the second mode, only selected central processing units requesting access to a resident datum are notified that it exists, while others requesting access to the datum are signalled that it does not exist. The common memory can include a plurality of independent memory elements, each coupled to and associated with, a respective one of the central processing units. A central processing unit can include a post-store element for effecting the transfer of copies of data stored in its associated memory element to a memory element associated with another central processing unit.

Abstract: A system and method for optimizing the performance of a computer memory system substitutes faster memory for a certain portion of the main memory. The substituted memory section automatically assumes a predesignated portion of the main memory and allows the main memory to become sequentially reorganized. Using this arrangement, for example, all the DOS applications that reside in the first 640 Kbytes of memory can be resident in the faster memory and the original main memory can then be used for other applications.

Abstract: A circuit for waking a microprocessor from a sleep mode and providing it with its microprocessor clock long enough for a refresh, direct memory access (DMA) or master cycle operation to be done by external circuitry. The clock signal is then removed from the microprocessor to put it back into the sleep mode, thereby conserving energy. A hold signal is provided to the microprocessor to cause the microprocessor outputs to be put into a tri-state, high impedance condition, and thus relinquish control of the external bus to the external refreshing circuitry.

Abstract: A method of dynamically managing the storage of information in a mass memory of a data processor is described. The mass memory includes a plurality of volumes of write-once media such as optical discs. The method involves grouping the volumes into volume sets, which each contain at least one file set, and dynamically increasing the size of the file sets and volume sets as needed during file storage. Update areas are set aside for each file set for modifications to the original data originally written into that file set. Allocation of storage to allow time-efficient access of files is accomplished by examining storage media characteristics, limits on file set size, and sizes of the data to be written into the file sets. Timers are set to indicate when volumes contain obsolete data and can be removed, when no additional data should be written onto volumes which are not obsolete, and when a volume should be flipped over so the other surface can be filled.

Abstract: An m-dimensional memory with m-1 dimensional hyperplane access. Random acs memory (RAM) circuits are arranged in a plurality of groups for storing data words corresponding to vertices of an m-dimensional lattice. Each vertex of the lattice is defined by an m-tuple. The minimum number of RAM circuits required to realize the memory architecture of the present invention is based upon the size of the lattice and the distribution of the data words in memory is based upon the m-tuples used to define the lattice.

Abstract: The present invention provides a memory interface system wherein there is provided a memory having multiple ports and divided into sections, with each section divided into subsections, with memory banks within each subsection, and the banks divided into at least two bank groups. The invention further provided a memory interface for controlling the referencing of said memory banks according to which bank group they are in.