Patents Examined by Reema Patel
  • Patent number: 10734260
    Abstract: A die sorting apparatus includes a fixing mechanism for fixing a wafer having a plurality of dies, a positioning mechanism including an indicator for selecting a die of the wafer using die coordinates, an ejection mechanism below the wafer for applying a force to the selected die, a moving mechanism mechanically coupled to the positioning mechanism and the ejection mechanism for aligning the positioning mechanism with the ejection mechanism according to the die coordinates. The ejection mechanism includes an ejection shaft, a pin driven by the ejection shaft to apply the force to the selected die, and a pin driving device for moving the pin up and down through the ejection shaft. The die sorting apparatus also includes a die pickup device mounted in parallel to or integrated in the positioning mechanism for picking up the selected die that is separated form the wafer through the pin.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 4, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chen Yang, Xin Xing Bai
  • Patent number: 10727315
    Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: July 28, 2020
    Assignee: Tessera, Inc.
    Inventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 10727270
    Abstract: A display device includes a substrate, and a first light-emitting diode element disposed over the substrate and having a first light-emitting path. The display device further includes a light-emitting angle changing layer disposed over the first light-emitting diode element. The display device further includes a second light-emitting diode element disposed over the substrate. The second light-emitting diode element is disposed at a position other than the region corresponding to the first light-emitting path. The first light-emitting diode element has a first light-emitting angle, the second light-emitting diode element has a second light-emitting angle, and the second light-emitting angle is greater than the first light-emitting angle.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 28, 2020
    Assignee: ACER INCORPORATED
    Inventors: Jui-Chieh Hsiang, Chih-Chiang Chen
  • Patent number: 10720608
    Abstract: A lighting device includes a substrate including a display area and a non-display area and an organic light emitting layer disposed in the display area. A first electrode is disposed on the organic light emitting layer and a second electrode is disposed below the organic light emitting layer. A phase change material layer is disposed below the second electrode and a plurality of third electrodes is disposed between the substrate and the phase change material layer. Therefore, a pattern having various colors of light and various shapes may be implemented based on a shape of the plurality of third electrodes, a phase change of the phase change material layer, and a color of light emitted from the organic light emitting layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 21, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sungwook Ko, Chiwan Kim
  • Patent number: 10720344
    Abstract: A method includes forming a semiconductor fin on a semiconductor substrate, the semiconductor fin comprising germanium, silicon, silicon germanium or any of III-V elements; forming a mask layer on a top portion of the semiconductor fin; and trimming the semiconductor fin, wherein trimming the semiconductor fin comprises: immersing the semiconductor substrate in a first electrolyte bath; and laterally removing a first portion of the semiconductor fin by supplying a first voltage to a counter electrode in the electrolyte bath and a second voltage to the semiconductor substrate, wherein the second voltage is negative.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Andrew Joseph Kelly, Yusuke Oniki
  • Patent number: 10714462
    Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 14, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind S. Bhagavat, Rahul Agarwal, Gabriel H. Loh
  • Patent number: 10714427
    Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 14, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Johannes Cornelis Jacobus De Langen, Marcel Nicolaas Jacobus van Kervinck, Vincent Sylvester Kuiper
  • Patent number: 10714533
    Abstract: A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: July 14, 2020
    Assignee: BRIDGELUX INC.
    Inventors: Mike Kwon, Gerry Keller, Scott West, Tao Tong, Babak Imangholi
  • Patent number: 10714353
    Abstract: A planarization method includes a grinding step of holding the opposite side to a separation surface in an SiC ingot by a rotatable chuck table and rotating a grinding wheel having plural grinding abrasives disposed in a ring manner to grind the separation surface of the SiC ingot held by the chuck table, and a flatness detection step of irradiating the separation surface of the SiC ingot exposed from the grinding wheel with light and detecting reflected light to detect the degree of flatness. The grinding step is ended when that the separation surface of the SiC ingot has become flat is detected in the flatness detection step.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 14, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kazuya Hirata
  • Patent number: 10716212
    Abstract: An inductor having an excellent Q values is provided with a configuration in which an inductor and a capacitor are integrally formed in a single element. Specifically, an LC device is provided that includes an element, an inductor, a capacitor, and a magnetic body portion. The element has a planar shape, and includes an insulating resin layer at at least part of the element. The inductor includes a loop-shaped conductor pattern and is formed inside the element. The capacitor is a mounting-type element, and is disposed in an opening of the loop-shaped conductor pattern and inside the element with at least a mounting surface of the capacitor being in contact with the resin layer. The magnetic body portion forms part of the element and is disposed between the conductor pattern and the capacitor over substantially an entire length of the loop-shaped conductor pattern.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 14, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Souko Fukahori, Toshiyuki Nakaiso, Akinori Hamada
  • Patent number: 10709009
    Abstract: One general aspect of the present disclosure includes an electrical circuit with a circuit carrier, at least one electrical component arranged on the circuit carrier, and at least one data transmission device with an antenna section. The data transmission device may be configured for wireless transmission of data and may include a housing, where the at least one electrical component, the at least one data transmission device, and at least one section of the circuit carrier are at least partially enclosed by the housing. At least the antenna section of the data transmission device may be arranged in a transmission range inside the housing and the transmission range may be spaced at a distance from the circuit carrier.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: July 7, 2020
    Assignee: ZF Friedrichshafen AG
    Inventor: Mathias Häuslmann
  • Patent number: 10707320
    Abstract: A method of forming a semiconductor device includes forming a hafnium-containing layer over a semiconductor layer, simultaneously performing a thermal annealing process and applying an electrical field to the hafnium-containing layer to form a ferroelectric hafnium-containing layer, and forming a gate electrode over the ferroelectric hafnium-containing layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming Lin, Kai Tak Lam, Sai-Hooi Yeong, Chi On Chui, Ziwei Fang
  • Patent number: 10707092
    Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
  • Patent number: 10707384
    Abstract: A light-emitting device includes a substrate including a base member having an upper surface having a substantially rectangular shape, a lower surface opposite to the upper surface, a first longer lateral surface, a second longer lateral surface opposite to the first longer lateral surface, a first shorter lateral surface, and a second shorter lateral surface opposite to the first shorter lateral surface, first wirings disposed on the upper surface, and second wirings disposed on the lower surface and each electrically connected with a respective one of the first wirings; at least one light-emitting element; and a light-reflective covering member covering lateral surfaces of the light-emitting element and the upper surface of the base member. The base member has at least one first recess open at the upper surface and the first longer lateral surface. Surfaces defining the at least one first recess are covered with the covering member.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: July 7, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Nakabayashi, Tadaaki Ikeda
  • Patent number: 10707435
    Abstract: Light-emitting elements such as LEDs are associated with light-converting material such as phosphor and/or other material. A donor substrate comprising the light-converting and/or other material is suitably placed relative to a target substrate associated with the light-emitting elements. A laser or other energy source is then used to transfer the light-converting and/or other material in a pattern via writing or masking from the donor substrate to the target substrate in accordance with the pattern. Addressability and targetability of the transfer process facilitates precise patterning of the target substrate.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: July 7, 2020
    Assignee: Quarkstar LLC
    Inventors: Ingo Speier, Robert C. Gardner, Louis Lerman, Christopher H. Lowery, Allan Brent York
  • Patent number: 10700058
    Abstract: Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10693054
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan, Benfu Lin
  • Patent number: 10679936
    Abstract: Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun huan Wei, Pin Yu Hsu, Szu-Yuan Chen, Po-June Chen, Kuan-Yu Chen
  • Patent number: 10681455
    Abstract: A microphone includes an acoustic element including an acoustic hole; a case disposed below the acoustic element and including an acoustic inlet formed in a position corresponding to the acoustic hole; and a plurality of through holes formed between the acoustic element and the case and formed in a position corresponding to the acoustic hole.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 9, 2020
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Hyunsoo Kim, Ilseon Yoo
  • Patent number: 10660154
    Abstract: A leveraged positioning system for installation of devices within campuses and buildings. A mobile device may have a position indicator associated with it. A campus or building information model may be available for reference relative to a location of the mobile device as noted by the position indicator. A location name may be derived from the model and used for an installed device since the mobile device is at the position of the installed device during placement of the installed device. A physical address may be assigned to the installed device. The physical address and the location name may be stored as a pair in memory for the device. Additional devices for installation may be treated similarly.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: May 19, 2020
    Assignee: Honeywell International Inc.
    Inventors: Gutha Stalin Sanghamitra, Patrick Gonia, Philipp Roosli, Bernard T. Geary