Patents Examined by Reema Patel
  • Patent number: 11127626
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jack Liu, Wei-Cheng Wu, Charles Chew-Yuen Young, Sing-Kai Huang
  • Patent number: 11127688
    Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The redistribution structure is electrically connected to the semiconductor die. The redistribution structure includes dielectric layers, conductive traces and seal patterns. The conductive traces are embedded in the dielectric layers. At least one conductive trace of the conductive traces includes a via pattern and a routing pattern. The seal patterns are disposed on the conductive traces. One seal pattern of the seal patterns is disposed between a top surface of the routing pattern and a first dielectric layer of the dielectric layers.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Hung-Jui Kuo, Ming-Tan Lee
  • Patent number: 11120993
    Abstract: A diffusing agent composition that can form a coating film in which the unevenness thereof is lowered, which is uniform and which has excellent stability, and a method of manufacturing a semiconductor substrate in which an impurity diffusing component is diffused into the semiconductor substrate from the coating film formed of the diffusing agent composition. An aliphatic amine which satisfies predetermined conditions is contained as an aliphatic amine compound in a diffusing agent composition including an impurity diffusing component. When the number of primary amino groups included in the amine compound is NA, the number of secondary amino groups included in the compound is NB, and the number of tertiary amino groups included in the amine compound is NC, NA, NB and NC satisfy predetermined formulas.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: September 14, 2021
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Keisuke Kubo, Yoshihiro Sawada, Shunichi Mashita
  • Patent number: 11121151
    Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: September 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shinhwan Kang, Younghwan Son, Haemin Lee, Kohji Kanamori, Jeehoon Han
  • Patent number: 11114572
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type embedded in the semiconductor layer, a first trench and a second trench formed in the semiconductor layer such that the first trench and the second trench penetrate the second semiconductor layer, a first insulating film formed on at least a side surface of the first trench, a second insulating film formed on at least a side surface of the second trench, a first sinker layer of the second conductivity type formed in a first portion of the semiconductor layer, a second sinker layer of the second conductivity type formed in the first portion of the semiconductor layer, a diode impurity region of the first conductivity type which is formed on the first surface of the semiconductor layer and forms a Zener diode by pn junction between the first sinker layer and the diode impurity region, a first wiring electrically connected to the diode impurity region, and a second wiring
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: September 7, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Yasushi Hamazawa
  • Patent number: 11107677
    Abstract: A SiC varied-growth-rate layer (2) is formed on a SiC bulk substrate (1) while increasing a growth speed from an initial growth speed of 2.0 ?m/h or less. A speed change rate of the SiC varied-growth-rate layer (2) is 720 ?m/h2 or less. A molar flow ratio of nitrogen to carbon when growth of the SiC varied-growth-rate layer (2) starts is 2.4 or less.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 31, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Susumu Hatakenaka
  • Patent number: 11107724
    Abstract: Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 11101149
    Abstract: A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Andrew Joseph Kelly, Yusuke Oniki
  • Patent number: 11101263
    Abstract: An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steve Edward Harrell, Keith Eric Sanborn, Wai Lee, Erika Lynn Mazotti
  • Patent number: 11094686
    Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, and first through fourth clock gate lines. The first power rail through third power rails are formed above the semiconductor substrate, and extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through fourth clock gate lines are formed above the semiconductor substrate, and extend in the second direction to pass through a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail. The first clock gate line and the second clock gate line are arranged to be adjacent to each other in the first direction, and the third clock gate line and the fourth clock gate line are arranged to be adjacent to each other in the first direction.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Su Kim
  • Patent number: 11094783
    Abstract: A semiconductor device includes: a diffusion layer of a second conductivity type provided on an upper layer portion of a semiconductor layer of a first conductivity type; a polysilicon added structure to be provided on the diffusion layer with a first silicon oxide film therebetween; a second silicon oxide film provided to have contact with an end surface of the polysilicon added structure, and having a gentle downward inclination from the end surface of the polysilicon added structure; and a third silicon oxide film provided on the diffusion layer with a predetermined distance from the end surface of the polysilicon added structure, and covered by the first silicon oxide film, wherein the first silicon oxide film is raised at a portion covering the third silicon oxide film, and constitutes a silicon oxide film with a gentle step-like surface layer formed of the portion raised and the second silicon oxide film.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 17, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinya Akao
  • Patent number: 11094670
    Abstract: A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Akshay N. Singh
  • Patent number: 11094681
    Abstract: A photocoupler of an embodiment includes a packaging member, a first and a second MOSFET, a semiconductor light receiving element, a semiconductor light emitting element, a first wiring part, and a sealing resin layer. The input terminal includes a first and a second lead. The output terminal includes a third and a fourth lead. The first conductive region includes a signal input part and a bend part. The fourth conductive region includes a signal input part and a bend part. The semiconductor light receiving element is joined to the first and second MOSFETs astride a gap part. The semiconductor light emitting element is joined onto a light receiving region. The first wiring part connects the source electrode of the first MOSFET and the source electrode of the second MOSFET.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 17, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Keita Saito, Naoya Takai
  • Patent number: 11094558
    Abstract: A method of manufacturing a doped metal chalcogenide thin film includes depositing a dopant atom on a base material; and forming a doped metal chalcogenide thin film on the dopant atom-deposited base material by supplying heat and a reaction gas comprising a metal precursor and a chalcogen precursor to the dopant atom-deposited base material.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 17, 2021
    Assignee: Research and Business Foundation Sungkyunkwan University
    Inventors: Changgu Lee, Youngchan Kim, Hunyoung Bark
  • Patent number: 11088241
    Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 10, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 11081344
    Abstract: Provided is a method for manufacturing a semiconductor substrate including: preparing a semiconductor substrate having a front surface on which an epitaxial layer has been formed; and forming a fracture layer on a rear surface of the semiconductor substrate before forming elements on the epitaxial layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 3, 2021
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Atsushi Fukugawa, Michiaki Murata
  • Patent number: 11081496
    Abstract: Embodiments of a method for forming three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is further formed by filling the channel hole with a channel-forming structure. The semiconductor channel may have a memory layer having a first memory portion surrounding a bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: August 3, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 11075159
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 11075290
    Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 27, 2021
    Assignees: Infineon Technologies AG, Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
  • Patent number: 11063044
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an isolation structure within a substrate. The isolation structure surrounds a device region of the substrate. A sacrificial gate material is formed over the isolation structure and the device region of the substrate. A part of the sacrificial gate material is removed and a second metal is deposited where the part of the sacrificial gate material was removed. A remainder of the sacrificial gate material is subsequently removed and a first metal is deposited where the remainder of the sacrificial gate material was removed. The first metal is different than the second metal.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu