Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode penetrating the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top surface and sidewalls of the storage structure, wherein the first shielding layer and the second shielding layer combine into one integrated shielding layer; and forming a second electrode which penetrates the shielding layer and electrically connects to the storage structure.

Abstract: Embodiments of the present disclosure relate to methods of fabricating conductive features to prevent metal extrusion. Particularly, the conductive feature includes a control layer to reduce grain size of a metal containing layer, thus obtaining a robust structure to decrease extrusion defects. In some embodiments, the control layer is formed between a barrier layer and the conductive feature. In some embodiments, the control layer is formed by adding a control element, such as oxygen, to an upper portion of the barrier layer.

Abstract: A semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer and having a side wall and a bottom wall, a field plate electrode formed in the trench, a gate electrode formed in the trench, and an insulation layer that isolates the field plate electrode and the gate electrode from each other and covers the side wall and the bottom wall in the trench. The semiconductor layer includes a drift region and a body region formed on the drift region. An interface of the drift region and the body region lies between a lower end position of the gate electrode and a reference position that is located upward from the lower end position by ? the thickness of the gate electrode in the depth direction.

Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

Abstract: The present disclosure provides a semiconductor device and a semiconductor layout structure. In the semiconductor device, a guard ring of a first type is arranged on at least one side of a transistor of a second type, and a guard ring of a second type is arranged on at least one side of a transistor of a first type, such that a plurality of signal lines in a first metal layer in the semiconductor layout structure may be arranged between a first power source line and a first ground line. Furthermore, in a second metal layer, a plurality of second power source lines are connected to one first power source line, and a plurality of second ground lines are connected to one first ground line.

Abstract: A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness hc.

Abstract: A semiconductor structure includes: a core device region and an anti-fuse device region, disposed on a same substrate; a first dielectric layer, disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant; a second dielectric layer, disposed on the first dielectric layer of the core device region; and a conductive layer, disposed on the second dielectric layer of the core device region and the first dielectric layer of the anti-fuse device region; wherein the second dielectric layer has a dielectric constant larger than the first dielectric constant.

Abstract: A method for depositing a metal oxynitride film by epitaxial growth at a low temperature is provided. It is a method for manufacturing a metal oxynitride film, in which the metal oxynitride film is epitaxially grown on a single crystal substrate by a sputtering method using an oxide target with a gas containing a nitrogen gas introduced. The oxide target contains zinc, the substrate during the deposition of the metal oxynitride film is higher than or equal to 80° C. and lower than or equal to 400° C., and the flow rate of the nitrogen gas is greater than or equal to 50% and lower than or equal to 100% of the total flow rate of the gas.

Abstract: A backside illuminated image sensor, including a semiconductor layer, a first gate structure, and a light sensing device, is provided. The semiconductor layer has a first surface and a second surface opposite to each other. The first gate structure is disposed on the second surface. The light sensing device is located in the semiconductor layer. The light sensing device extends from the first surface to the second surface.

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

Abstract: The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 ?. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.

Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

Abstract: An array substrate, a method for manufacturing the array substrate and a display device. The array substrate includes: a base substrate including a display region and a peripheral region surrounding the display region; and a light-leakage protection film layer formed on the base substrate. The light-leakage protection film layer is arranged at the peripheral region and includes at least one first film layer, a light transmittance of each first film layer is smaller than or equal to a first threshold, and reflectivity of the first film layer is smaller than or equal to a second threshold.

Abstract: A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: A semiconductor device comprising a semiconductor substrate having upper and lower surfaces and a hydrogen containing region containing hydrogen and a lifetime control region is provided. The carrier concentration distribution of the hydrogen containing region has: a first local maximum point; a second local maximum point closest to the first local maximum point among local maximum points positioned between the first local maximum point and the upper surface; a first intermediate point of the local minimum between the first and second local maximum points; and a second intermediate point closest to the second local maximum point among local minimum points or flat points where the carrier concentration remains constant positioned between the second local maximum point and the upper surface. The lifetime control region is positioned at least between the first and second local maximum points. The first intermediate point has a lower carrier concentration than the second intermediate point.

Abstract: Methods of manufacture and memory cells manufactured according to the methods are described. The manufacture has a lower thermal budget and experiences less heating by including a blocking layer including MgO. The method of manufacture may include annealing following deposition of the MgO, with the annealing occurring at temperatures below 900° C. or below 800° C. The blocking layers may be a first blocking layer made of SiO2 and a second blocking layer made of MgO. The memory cells may have a CMOS Under Array (CuA) structure. The memory cells may be part of a three-dimensional NAND memory device.

Abstract: A substrate stripping method and an epitaxial wafer, relating to the technical field of semiconductors. The method comprises: providing a substrate (1), the substrate (1) having a recess, and the recess being distributed on a first surface (1a) of the substrate (1); forming a hydrophilic layer (3) in the recess; forming, on the first surface (1a), an etching sacrificial layer (4) covering the first surface (1a), the etching sacrificial layer (4) and the recess defining a flowing space (A); growing an epitaxial layer (5) on the etching sacrificial layer (4); and soaking the etching sacrificial layer (4) and the substrate (1) in an etching liquid, and corroding the etching sacrificial layer (4) by means of the etching liquid until the epitaxial layer (5) is separated from the substrate (1). The method can rapidly and uniformly etch the etching sacrificial layer (4).