Abstract: A backside illuminated image sensor, including a semiconductor layer, a first gate structure, and a light sensing device, is provided. The semiconductor layer has a first surface and a second surface opposite to each other. The first gate structure is disposed on the second surface. The light sensing device is located in the semiconductor layer. The light sensing device extends from the first surface to the second surface.

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

Abstract: The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 ?. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.

Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

Abstract: An array substrate, a method for manufacturing the array substrate and a display device. The array substrate includes: a base substrate including a display region and a peripheral region surrounding the display region; and a light-leakage protection film layer formed on the base substrate. The light-leakage protection film layer is arranged at the peripheral region and includes at least one first film layer, a light transmittance of each first film layer is smaller than or equal to a first threshold, and reflectivity of the first film layer is smaller than or equal to a second threshold.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: A semiconductor device comprising a semiconductor substrate having upper and lower surfaces and a hydrogen containing region containing hydrogen and a lifetime control region is provided. The carrier concentration distribution of the hydrogen containing region has: a first local maximum point; a second local maximum point closest to the first local maximum point among local maximum points positioned between the first local maximum point and the upper surface; a first intermediate point of the local minimum between the first and second local maximum points; and a second intermediate point closest to the second local maximum point among local minimum points or flat points where the carrier concentration remains constant positioned between the second local maximum point and the upper surface. The lifetime control region is positioned at least between the first and second local maximum points. The first intermediate point has a lower carrier concentration than the second intermediate point.

Abstract: Methods of manufacture and memory cells manufactured according to the methods are described. The manufacture has a lower thermal budget and experiences less heating by including a blocking layer including MgO. The method of manufacture may include annealing following deposition of the MgO, with the annealing occurring at temperatures below 900° C. or below 800° C. The blocking layers may be a first blocking layer made of SiO2 and a second blocking layer made of MgO. The memory cells may have a CMOS Under Array (CuA) structure. The memory cells may be part of a three-dimensional NAND memory device.

Abstract: A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.

Abstract: A substrate stripping method and an epitaxial wafer, relating to the technical field of semiconductors. The method comprises: providing a substrate (1), the substrate (1) having a recess, and the recess being distributed on a first surface (1a) of the substrate (1); forming a hydrophilic layer (3) in the recess; forming, on the first surface (1a), an etching sacrificial layer (4) covering the first surface (1a), the etching sacrificial layer (4) and the recess defining a flowing space (A); growing an epitaxial layer (5) on the etching sacrificial layer (4); and soaking the etching sacrificial layer (4) and the substrate (1) in an etching liquid, and corroding the etching sacrificial layer (4) by means of the etching liquid until the epitaxial layer (5) is separated from the substrate (1). The method can rapidly and uniformly etch the etching sacrificial layer (4).

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Abstract: An integrated circuit includes a set of power rails, a set of active regions, a first set of conductive lines and a first and a second set of vias. The set of power rails is configured to supply a first or second supply voltage, and is on a first level of a back-side of a substrate. The set of active regions is a second level of a front-side of the substrate. The first set of conductive lines extend in a second direction and overlap the set of active regions. The first set of vias is between and electrically couples the set of active regions and the first set of conductive lines together. The second set of vias is between and electrically couples the first set of conductive lines and the set of power rails together.

Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

Abstract: The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

Abstract: A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and a gate electrode surrounding the interfacial layer.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion.

Abstract: Embodiments relate to a semiconductor device, which includes: a substrate made of a first material; an insulating layer formed on an upper surface of the substrate; a trench formed at the insulating layer to penetrate the insulating layer toward the substrate; and a seed layer disposed in the trench. The seed layer is made of a second material, the second material lattice-mismatches with respect to the first material, the seed layer includes a threading dislocation extending at least partially in a first direction non-parallel to the upper surface of the substrate and parallel to a <110> direction of a (111) plane and a threading dislocation extending at least partially in a second direction, and the extension of the threading dislocation is terminated at a sidewall of the trench.

Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.