Patents Examined by Reema Patel
  • Patent number: 11515172
    Abstract: In a first aspect of a present inventive subject matter, a method of etching an object to be etched with an etching liquid that contains bromine, and the object contains at least gallium and/or aluminum.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 29, 2022
    Assignee: FLOSFIA INC.
    Inventor: Isao Takahashi
  • Patent number: 11515355
    Abstract: A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LIMITED
    Inventors: Yeh-Hsun Fang, Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai
  • Patent number: 11508623
    Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
  • Patent number: 11508820
    Abstract: A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness hc.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 22, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., iBeam Materials, Inc.
    Inventors: Junhee Choi, Joohun Han, Vladimir Matias
  • Patent number: 11502102
    Abstract: Embodiments of a method for forming a three-dimensional (3D) memory device includes the following operations. First, a channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. A semiconductor channel is formed by filling the channel hole with a channel-forming structure. The plurality of first layers is removed. A plurality of conductor layers is formed from the plurality of second layers. Further, a gate-to-gate dielectric layer is formed between the adjacent conductor layers, the gate-to-gate dielectric layer including at least one sub-layer of silicon oxynitride.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: November 15, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 11502019
    Abstract: One example heat sink includes a heat dissipation substrate, a connector, and a fastener. The heat dissipation substrate is configured to dissipate heat for a packaged chip located on a circuit board, and the heat dissipation substrate is located on a surface that is of the packaged chip and that is opposite to the circuit board. A first heat dissipation substrate and a second heat dissipation substrate of the heat dissipation substrate each have a heat conduction surface that conducts heat with a chip in the packaged chip. Different heat conduction surfaces correspond to different chips.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: November 15, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shoubiao Xu, Shanjiu Chi, Wenhui Zeng
  • Patent number: 11495489
    Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuan-Liang Liu, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 11482584
    Abstract: A display apparatus including a shielding conductive layer is disclosed. The display apparatus includes a substrate, a driving thin film transistor disposed on the substrate, wherein the driving thin film transistor includes a driving semiconductor layer and a driving gate electrode, a scan line overlapping the substrate and extending in a first direction, a data line extending in a second direction crossing the first direction, wherein the data line is insulated from the scan line by an insulating layer, a node connection line disposed on a same layer as the scan line, and a shielding conductive layer disposed between the data line and the node connection line, in which a first end of the node connection line is connected to the driving gate electrode via a first node contact hole.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Wonse Lee, Kyunghoon Kim
  • Patent number: 11482532
    Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: October 25, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
  • Patent number: 11476415
    Abstract: Aspects of the invention are directed to a method of forming an integrated circuit. Both a dielectric layer and a bottom contact are formed with the bottom contact disposed at least partially in the dielectric layer. The bottom contact is subsequently recessed into the dielectric layer to cause the dielectric layer to define two sidewalls bordering regions of the bottom contact removed during recessing. Two sidewall spacers are then formed along the two sidewalls. A landing pad is formed on the recessed bottom contact and between the two sidewall spacers. Lastly, an additional feature is formed on top of the landing pad at least in part by anisotropic etching. In one or more embodiments, the additional feature includes a magnetic tunnel junction patterned at least in part by ion beam etching.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kisup Chung, Michael Rizzolo, Fee Li Lie
  • Patent number: 11476111
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 18, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 11469320
    Abstract: A semiconductor device includes a source region and a drain region formed in a substrate and having different conductivity types, an insulating film formed between the source region and the drain region, a deep well region formed under the insulating film, and a pinch-off region formed under the insulating film and having a same conductivity type as the deep well region, wherein a depth of a bottom surface of the pinch-off region is different from a depth of a bottom surface of the deep well region.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 11, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventor: Young Bae Kim
  • Patent number: 11469175
    Abstract: The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a bottom conductive layer positioned in the substrate, an insulation layer positioned on the substrate, a first conductive layer positioned on the insulation layer and above the bottom conductive layer, a second conductive layer positioned on the insulation layer and above the bottom conductive layer and spaced apart from the first conductive layer, a conductive plug electrically coupled to the bottom conductive layer, and a top conductive layer electrically coupled to the first conductive layer and the second conductive layer. The first conductive layer has a first work function and the second conductive layer has a second work function different from the first work function. The bottom conductive layer, the insulation layer, the first conductive layer, and the second conductive layer together configure a programmable unit.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: October 11, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Hsih-Yang Chiu, Tse-Yao Huang
  • Patent number: 11462565
    Abstract: Embodiments of a method for forming three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is further formed by filling the channel hole with a channel-forming structure. The semiconductor channel may have a memory layer having a first memory portion surrounding a bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: October 4, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 11450688
    Abstract: Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: September 20, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 11450525
    Abstract: Methods of depositing films are described. Specifically, methods of depositing metal oxide films are described. A metal oxide film is selectively deposited on a metal layer relative to a dielectric layer by exposing a substrate to an organometallic precursor followed by exposure to an oxidant.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 20, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Liqi Wu, Hung Nguyen, Bhaskar Jyoti Bhuyan, Mark Saly, Feng Q. Liu, David Thompson
  • Patent number: 11450702
    Abstract: An image sensor device which can reduce a chip size and power consumption, is disclosed. The image sensor device includes a substrate provided with a first surface and a second surface that are arranged to face each other, a pad disposed at the first surface of the substrate, a line layer disposed below the second surface of the substrate, a first through silicon via (TSV) formed to penetrate the substrate and the line layer, and disposed at one side of the pad, a second TSV formed to penetrate the substrate and the line layer, and disposed at the other side of the pad, and a power-supply switch disposed between the first TSV and the second TSV.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Young Guk Lee
  • Patent number: 11424336
    Abstract: A system and method for laying out power grid connections for standard cells are described. In various implementations, gate metal is placed over non-planar vertical conducting structures, which are used to form non-planar devices (transistors). Gate contacts connect gate metal to gate extension metal (GEM) above the gate metal. GEM is placed above the gate metal and makes a connection with gate metal through the one or more gate contacts. Gate extension contacts are formed on the GEM above the active regions. Similar to gate contacts, gate extension contacts are formed with a less complex fabrication process than using a self-aligned contacts process. Gate extension contacts connect GEM to an interconnect layer such as a metal zero layer. Gate extension contacts are aligned vertically with one of the non-planar vertical conducting structures. Therefore, in an implementation, one or more gate extension contacts are located above the active region.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 23, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 11424366
    Abstract: A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and in which the high-k dielectric layer is in contact with the top surface of the STI structure.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11417529
    Abstract: A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 16, 2022
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Yuji Zhao, Houqiang Fu, Kai Fu