Patents Examined by Regan J Rundio
  • Patent number: 10181400
    Abstract: A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 15, 2019
    Assignee: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Patent number: 10056383
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Patent number: 10050166
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10043718
    Abstract: A method of fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a fin structure thereon; forming a recess in the fin structure so that the semiconductor substrate is partially exposed from the bottom surface of the recess; forming a dopant source layer conformally disposed on side surfaces and a bottom surface of the recess; removing the dopant source layer disposed on the bottom surface of the recess until portions of the semiconductor substrate are exposed from the bottom surface of the recess; and annealing the dopant source layer so as to form a side doped region in the fin structure.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Hung Chen, Rung-Yuan Lee, Chun-Tsen Lu, Chorng-Lih Young
  • Patent number: 10032936
    Abstract: A method for manufacturing a resistive element includes: preparing a substrate including an n-type silicon layer; doping the silicon layer with an impurity to thereby form a resistive region; heat-treating the resistive region by any of rapid thermal annealing, flash lamp annealing, and excimer laser annealing; and epitaxially growing silicon on the resistive region to thereby form a covering layer.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: July 24, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Patent number: 10008447
    Abstract: A semiconductor device includes a circuitry die and a solar cell die. The circuitry die includes a plurality of interconnect layers on a front side of the circuitry die, a metallization layer on a back side of the circuitry die, and at least one TSV (through substrate via) that makes an electrical connection between a last metal interconnect layer on the front side of the circuitry die and the metallization layer on the back side of the circuitry die. The solar cell die is configured to power the circuitry die. The solar cell die includes a transparent contact on a front side of the solar cell die. A back side of the solar cell die is attached to the back side of the circuitry die and makes electrical contact with the metallization layer on the back side of the circuitry die.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 26, 2018
    Assignee: NXP USA, Inc.
    Inventors: Douglas M. Reber, Mehul D. Shroff
  • Patent number: 10002765
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Patent number: 9991390
    Abstract: A coated substrate including a thin film of a transition metal dichalcogenide and associated methods are shown. In one example, the substrate is a semiconductor wafer. In one example, the thin film is atomically thin, and the substrate is a number of centimeters in diameter. In one example a crystalline structure of the thin film is substantially 2H hexagonal.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 5, 2018
    Assignee: The Regents of the University of California
    Inventors: Aaron S. George, Robert Ionescu, Hamed Hosseini Bay, Mihrimah Ozkan, Cengiz S Ozkan
  • Patent number: 9991434
    Abstract: A semiconductor device includes an insulating substrate,a semiconductor element disposed on an upper surface of the substrate, a heat dissipation member, and a metal bonding layer that bonds the lower surface of the substrate to the upper surface of the heat dissipation member, and the area of the upper surface of the heat dissipation member is larger than the area of the lower surface of the substrate, and the metal bonding layer contacts the whole of the lower surface of the substrate and has an area larger than the area of the lower surface of the substrate, and the heat conductivity of the metal bonding layer is higher than the heat conductivity of the heat dissipation member.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 5, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Masatsugu Ichikawa, Satoshi Shichijo, Takehito Shimatsu
  • Patent number: 9984884
    Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 29, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 9978873
    Abstract: The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the STI not covered by the gate structure are etched, until the STI is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9972540
    Abstract: Method for fabricating semiconductor device comprising: forming a dummy gate on a first nitrided oxide layer and a non-nitrided oxide layer; nitridizing an exposed section of the non-nitrided oxide layer to form a second nitrided oxide layer; forming an interlayer dielectric on the first nitrided oxide layer and the second nitrided oxide layer; removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening; removing the dummy gate from the non-nitrided oxide layer to form a second opening with a non-nitrided portion of oxide layer exposed in the second opening; removing the non-nitrided portion of the oxide layer; forming a first dielectric layer and first metal gate material in the first opening; and forming a second dielectric layer and second metal gate material in the second opening.
    Type: Grant
    Filed: August 7, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9966315
    Abstract: Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Philipp Jaschinsky, Frank Kahlenberg, Sirko Kramp, Roberto Schiwon, Rolf Seltmann
  • Patent number: 9960080
    Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly. The IC device or devices in the upper wafer or wafers have contact structures that serve as masks for the etching of the TSV opening. A conformal isolation liner is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug in the TSV opening. The removal of the liner is done without applying a lithography step.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 1, 2018
    Assignee: IMEC vzw
    Inventor: Eric Beyne
  • Patent number: 9941227
    Abstract: A package is provided. The package comprises a die and an impedance matching network. The die has a first terminal and a second terminal. The impedance matching network is coupled to the second terminal and comprises a first inductor and a first capacitor. The first inductor comprises first bond wire connections coupled between the second terminal and a first bond pad on the die, and second bond wire connections coupled between the first bond pad and a second bond pad coupled to the first capacitor.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 10, 2018
    Assignee: Ampleon Netherlands B.V.
    Inventors: Yi Zhu, Josephus Van Der Zanden, Iouri Volokhine, Rob Mathijs Heeres
  • Patent number: 9929210
    Abstract: A spin-orbit torque magnetic random access memory includes a substrate, and an SOT memory cell disposed on the substrate and including a magnetic free layer including a ferromagnetic first metal layer, an anti-ferromagnetic second metal layer, and a third metal layer for generating spin-Hall effect. The first metal layer has a thickness ranging from 0.5 nm to 1.5 nm and exhibits perpendicular magnetic anisotropy (PMA). The second metal layer has a thickness greater than 6 nm for providing an exchange bias field. The second metal layer is an IrMn layer not undergone out-of-plane magnetic annealing or coating and exhibiting no PMA. The magnetic free layer has a coercive magnetic field (Hc) upon reaching the critical current density, and |HEB|>|Hc|.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: March 27, 2018
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chih-Huang Lai, Ming-Han Tsai, Kuo-Feng Huang
  • Patent number: 9923064
    Abstract: A vertical semiconductor device includes a semiconductor body having a front side, a backside arranged opposite to the front side and a lateral edge delimiting the semiconductor body in a horizontal direction perpendicular to the front side, a gate metallization arranged on the front side and extending at least close to the lateral edge; a contact metallization arranged on the front side and between the lateral edge and the gate metallization, and a backside metallization arranged on the backside and in electric contact with the contact metallization. The gate metallization is arranged around at least two sides of the contact metallization when viewed from above.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Rudolf Rothmaler
  • Patent number: 9923060
    Abstract: A method cold-melts a high conductivity region between a high-resistivity silicon substrate and a gallium-nitride layer to form a trap rich region that substantially immobilizes charge carriers in that region. Such a process should substantially mitigate the parasitic impact of that region on circuits formed at least in part by the gallium-nitride layer.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: March 20, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Shrenik Deliwala, James Fiorenza, Donghyun Jin
  • Patent number: 9917129
    Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: March 13, 2018
    Assignee: SONY CORPORATION
    Inventors: Takashi Yokoyama, Taku Umebayashi
  • Patent number: 9916936
    Abstract: A method for forming conductive electrode patterns of a solar cell is provided. The method includes preparing a glass substrate and forming a transparent conductive oxide film (TCO) on the glass substrate. Then, a titanium oxide (TiO2) layer and a silver (Ag) electrode are formed on the glass substrate. A nickel (Ni) layer is formed on the Ag electrode and a copper (Cu) layer is formed on the Ni layer. In addition, a tin (Sn) layer is formed on the Cu layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 13, 2018
    Assignee: Hyundai Motor Company
    Inventor: Kyoung Jin Jeong