Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a plurality of electrode layers; a semiconductor film; a charge storage film; an interconnect layer provided in the stacked body, the interconnect layer; a first contact portion; a first metal layer; and a second metal layer. The interconnect layer includes: a first portion including silicon; and a second portion provided on the first portion and including metal. The first metal layer is provided on the first contact portion. The second metal layer is provided on the first metal layer, and electrically connected to the interconnect layer.

Abstract: To provide a semiconductor device having a structure with which the device can be easily manufactured even if the size is decreased and which can suppress a decrease in electrical characteristics caused by the decrease in the size, and a manufacturing method thereof. A source electrode layer and a drain electrode layer are formed on an upper surface of an oxide semiconductor layer. A side surface of the oxide semiconductor layer and a side surface of the source electrode layer are provided on the same surface and are electrically connected to a first wiring. Further, a side surface of the oxide semiconductor layer and a side surface of the drain electrode layer are provided on the same surface and are electrically connected to a second wiring.

Abstract: Provided is a 3DIC structure including first and second IC chips and connectors. The first IC chip includes a first metallization structure, a first optical active component, and a first photonic interconnection layer. The second IC chip includes a second metallization structure, a second optical active component, and a second photonic interconnection layer. The first and second IC chips are bonded via the first and second photonic interconnection layers. The first optical active component is between the first photonic interconnection layer and the first metallization structure. The first optical active component and the first metallization structure are bonded to each other. The second optical active component is between the second photonic interconnection layer and the second metallization structure. The second optical active component and the second metallization structure are bonded to each other.

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, a semiconductor region can be formed in or above a substrate. A first metal layer can be formed over the semiconductor region. A laser can be applied over a first region of the metal layer to form a first metal weld between the metal layer and the semiconductor region, where applying a laser over the first region comprises applying the laser at a first scanning speed. Subsequent to applying the laser over the first region, the laser can be applied over a second region of the metal layer where applying the laser over the second region includes applying a laser at a second scanning speed. Subsequent to applying the laser over the second region, the laser can be applied over a third region of the metal layer to form a second metal weld, where applying the laser over the third region comprises applying the laser at a third scanning speed.

Abstract: A FinFET is provided. The FinFET includes a substrate. A plurality of fin structures are defined on the substrate. A gate structure crosses each fin structure. Two first recesses are disposed on two sides of the gate structure respectively, wherein each first recess further includes a plurality of second recesses disposed therein, and the position of each second recess corresponds to each fin structure. Two epitaxial layers are disposed at two sides of the gate structure respectively and in the first recesses, each epitaxial layer has a bottom surface including a second concave and convex profile, and each epitaxial layer directly contacts a bottom surface of each first recess and a bottom surface of each second recess.

Abstract: This disclosure discloses a light-emitting device. The light-emitting device includes: a heat-dissipating structure having a first part and a second part separated from the first part; a light-emitting unit including a light-emitting element with a first pad formed on the first part; and a first transparent enclosing the light-emitting element and having a sidewall; and an adhesive material covering a portion of the sidewall.

Abstract: A semiconductor device includes a P-type substrate, and an N-well in the P-type substrate. A first N+ diffusion region is located in the P-type substrate, and a first P+ diffusion region is located in the N-well. A second P+ diffusion region is located across a boundary between the P-type substrate and the N-well. A first gate electrode overlies the N-well between the first P+ diffusion regions and the second P+ diffusion region. A second gate electrode overlies the P-type substrate between the second P+ diffusion region and the first N+ diffusion region. The first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device. The first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS transistor. The second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode.

Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, a first and second semiconductor regions can be formed in or above a substrate, where a separation region is disposed between the first and second semiconductor regions. A protective region can be formed over the separation region. A first metal layer can be formed over the substrate, where the protective region prevents and/or inhibits damage to the separation region during the formation of the first metal layer. Conductive contacts can be formed over the first and second semiconductor regions.

Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a first shallow trench isolation (STI) around the fin-shaped structure; dividing the fin-shaped structure into a first portion and a second portion; and forming a second STI between the first portion and the second portion.

Abstract: A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.

Abstract: A spin valve magnetoresistance element has an even number of free layer structures for which half has an antiferromagnetic coupling and the other half has a ferromagnetic coupling with respect to associated pinned layers. The different couplings are the result of an even number different spacer layers having respective different thicknesses.

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Abstract: Provided is a method of manufacturing an organic light emitting device, the method including forming a lower electrode on a lower substrate, forming an organic layer on the lower electrode, forming a light extraction layer including an adhesion layer and nanoparticles on an upper substrate, forming an upper electrode on the light extraction layer, and coupling the lower substrate to the upper substrate so that the upper electrode contacts the organic layer. The forming of the light extraction layer includes providing an adhesive between a first sacrificial substrate and the upper substrate, curing the adhesive to form the adhesion layer to form the adhesion layer, and removing the first sacrificial substrate to expose the adhesion layer. The first sacrificial substrate and the upper substrate are coupled to each other by the adhesion layer.

Abstract: A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride.

Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.

Abstract: An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

Abstract: An LED light emitting device 5 as an example of a light emitting device utilizing a semiconductor to which the present invention is applied includes a package 10, a semiconductor light emitting element 200, a first sealing layer 50, and a second sealing layer 60. The semiconductor light emitting element 200 includes a p-n functioned semiconductor layer, and serves as a light source that emits light in accordance with application of a voltage to the semiconductor layer. The semiconductor light emitting element 200 is connected to power supply terminals 201 that supply a current.

Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.