Abstract: A semiconductor body of an IGBT includes: a first base region of a second conductivity type; a source region of a first conductivity type different from the second conductivity type and forming a first pn-junction with the first base region; a drift region of the first conductivity type and forming a second pn-junction with the first base region; a collector region of the second conductivity type; at least one trench filled with a gate electrode and having a first trench portion of a first width and a second trench portion of a second width, the second width being different from the first width; and a field stop region having the first conductivity type and located between the drift region and the collector region. The field stop region includes a plurality of buried regions having the second conductivity type.

Abstract: The invention relates to a method of manufacturing a I-III-VI2 layer with photovoltaic properties, comprising: deposition of a metal on a substrate to form a contact layer, deposition of a precursor of the photovoltaic layer, on the contact layer, and heat treatment of the precursor with an addition of element VI to form the I-III-VI2 layer. The element VI usually diffuses into the contact layer (MO) during the heat treatment and combines with the metal to form a superficial layer (SUP) on the contact layer. In the method of the invention, the metal deposition comprises a step during which an additional element is added to the metal to form a compound (MO-EA), in the contact layer, acting as a barrier to the diffusion of the element VI, which allows precisely controlling the properties of the superficial layer, particularly its thickness.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

Abstract: A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously.

Abstract: A TI-IGBT, comprising a first semiconductor substrate, a second semiconductor substrate, and a first doped layer; a short circuit region and a collector region disposed in parallel are formed in the first semiconductor substrate; the short circuit region and the collector region have different doping types; the second semiconductor substrate is located on the upper surface of the first semiconductor substrate, and has the same doping type with the short circuit region; the first doped layer is located between the first semiconductor substrate and the second semiconductor substrate, and covers at least the collector region; the first doped layer has the same doping type with the second semiconductor substrate, and has a doping concentration smaller than that of the second semiconductor substrate.

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P?45?0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Abstract: A multi-junction solar cell is provided and includes multiple semiconducting layers and an interface layer disposed between the multiple semiconducting layers. The interface layer is made from an interface bonding material that has a refractive index such that a ratio of a refractive index of each of the multiple semiconducting layers to the refractive index of the interface bonding material is less than or equal to 1.5.

Abstract: An interposer sheet can be used for making semiconductor bodies, such as of silicon, such as for solar cell use. It is free-standing, very thin, flexible, porous and able to withstand the chemical and thermal environment of molten semiconductor without degradation. It is typically of a ceramic material, such as silica, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride and others. It is provided between a forming surface of a mold sheet, and the molten material from which a semiconductor body will be formed. It may be secured to the forming surface or deposited upon the melt. The interposer sheet suppresses grain nucleation, and limits heat flow from the melt. It promotes separation of the semiconductor body from the forming surface. It can be fabricated before its use. Because free-standing and not adhered to the forming surface, problems of mismatch of CTE are minimized.

Abstract: A method for manufacturing a semiconductor device includes processes of: (a) implant first conductivity type first impurities in a first region of a first surface; (b) form a second conductivity type semiconductor region exposed in the second region of the first surface by implanting second conductivity type second impurities in the second region; (c) implant charged particles at a dose amount larger than those of the first and the second impurities in a third region of the first surface which at least partially overlaps with the first region and is adjacent to the second region so that an implantation depth of the charged particles becomes shallower than that of the first impurities. After having performed the processes of (a) to (c), a metal is deposited on the second and the third regions, and the metal is caused to react with the semiconductor substrate to form the silicide layer.

Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

Abstract: In various embodiments, a solar cell screen-printing composition is provided, comprising aluminum; and silicon; the percentage by mass of silicon lying in a range from 5% to 95% of the sum of the percentages by mass of silicon and aluminum.

Abstract: A light emitting device includes a substrate, a light-emitting diode chip mounted on the substrate, a Zener diode chip mounted next to the light-emitting diode chip on the substrate, a frame-like dam material formed on the substrate to surround the light-emitting diode chip and the Zener diode chip, and a light-reflective resin injected inside the dam material to coat side surfaces of the light-emitting diode chip and side surfaces and an upper surface of the Zener diode chip. A part of the frame-like dam material swells outward to surround three of the side surfaces of the Zener diode chip.

Abstract: To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.

Abstract: A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.

Abstract: A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) surrounds the exposed topography. Further to the method, the template is filled with a block copolymer (BCP) to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography.

Abstract: A light emitting device according to embodiments includes a light emitting element emitting light with a peak wavelength of 420˜445 nm, a first phosphor emitting light with a peak wavelength of 485˜530 nm, a second phosphor emitting light with a peak wavelength of 530˜580 nm, and a third phosphor emitting light with a peak wavelength of 600˜650 nm. The device emits light having an emission spectrum that has a local minimum value of light intensity between a wavelength of 450˜470 nm or less, the local minimum value being 60% or less of a maximum value of light intensity at a longer wavelength side from the local minimum value, and the device emits light having a color temperature of 4600 K or higher and 5400 K or less.

Abstract: The aim of the present invention is to provide a semiconductor device containing a graphene p-n vertical tunneling-junction diode by assessing the optical and electrical characteristics of a graphene p-n junction produced by varying the doping concentration. The semiconductor device includes first graphene of a first doping type, and second graphene of a second doping type different from the first doping type, which is arranged on the first graphene and is in contact therewith.

Abstract: To provide a semiconductor device having a structure with which the device can be easily manufactured even if the size is decreased and which can suppress a decrease in electrical characteristics caused by the decrease in the size, and a manufacturing method thereof. A source electrode layer and a drain electrode layer are formed on an upper surface of an oxide semiconductor layer. A side surface of the oxide semiconductor layer and a side surface of the source electrode layer are provided on the same surface and are electrically connected to a first wiring. Further, a side surface of the oxide semiconductor layer and a side surface of the drain electrode layer are provided on the same surface and are electrically connected to a second wiring.