Patents Examined by Reginald Bragdon
  • Patent number: 9542106
    Abstract: Dynamically creates a cloned target volume by cloning a production volume without breaking a Flashcopy chain for continuing an ingestion of a Flashcopy backup target volume.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay H. Akirav, Joseph W. Dain, Gregory T. Kishi, Osnat Shasha
  • Patent number: 9535617
    Abstract: Upon an indication that a Flashcopy backup is not to be ingested, ingesting changed grains and/or a Flashcopy Map (fcmap) of the Flashcopy backup into a repository and dynamically marking the Flashcopy backup for collapse from a first repository into a second repository without breaking a flashcopy chain.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph W. Dain, Gregory T. Kishi, Christopher Zaremba
  • Patent number: 9529537
    Abstract: A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: December 27, 2016
    Assignee: HITACHI, LTD.
    Inventors: Atsushi Kawamura, Junji Ogawa
  • Patent number: 9529547
    Abstract: A memory device comprising a memory controller and a homogeneous memory accessible by the memory controller, wherein the homogeneous memory is divided by the memory controller in a first memory partition and a second memory partition, wherein the first memory partition is allocated to a first type of information comprising user data and ECC data that are arranged interleaved with the user data, and wherein the second memory partition is allocated to a second type of information comprising further user data.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: December 27, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Staudenmaier, Vincent Aubineau, Iosef E. Martinez-Pelayo
  • Patent number: 9529709
    Abstract: A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: December 27, 2016
    Assignee: SILICON MOTION, INC.
    Inventors: Chi-Lung Wang, Chia-Hsin Chen, Chien-Cheng Lin
  • Patent number: 9529540
    Abstract: Accesses to a number of data blocks stored in a distributed storage are observed. Following observation of the accesses, the stored data blocks are redistributed. In one aspect, redistribution of the data blocks includes determining the access patterns for one or more of the data blocks based on the observed accesses, and determining the storage sizes for the one or more data blocks. Thereafter, based on the determined access patterns and determined storage sizes, the one or more data blocks are sorted. Subsequently, the one or more data blocks are redistributed or rebalanced across a number of storage devices of the distributed storage based on the sorting. In one aspect, the one or more data blocks are redistributed according to either a uniform distribution scheme or a proportional distribution scheme.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 27, 2016
    Assignee: Quantcast Corporation
    Inventors: Silvius V. Rus, Michael Ovsiannikov
  • Patent number: 9524401
    Abstract: There is provided a method for providing access to data securely stored in memory card. An exemplary method comprises specifying first time information corresponding to a time period and storing the first time information in the memory card. The exemplary method also comprises inserting the memory card into a terminal. The exemplary method additionally comprises determining in a control unit included in the memory card, whether the time period has lapsed. The exemplary method also comprises allowing the terminal to access the data until it is determined that the time period has lapsed.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: December 20, 2016
    Assignee: Vodafone Holding GMBH
    Inventors: Najib Koraichi, Sebastiaan Hoeksel
  • Patent number: 9519534
    Abstract: An information processing apparatus includes a processor, a first memory, and a second memory, wherein the second memory includes a first data storage region having a first data capacity and a second data storage region having a second data capacity smaller than the first data capacity, and the processor is configured to, in a case of executing first processing, select the first data storage region as a storage region for data to be written into the second memory by the first processing, and select the second data storage region as a storage region for data to be written into the second memory by second processing, and in a case of not executing the first processing, select the first data storage region as a storage region for data to be written from the first memory to the second memory by the second processing.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 13, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Masatoshi Sugino
  • Patent number: 9519615
    Abstract: A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 Tera Bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: December 13, 2016
    Assignee: EMC Corporation
    Inventors: Frederic Roy Carlson, Jr., Mark Himelstein, Bruce Wilford, Dan Arai, David R. Emberson
  • Patent number: 9514040
    Abstract: A memory storage device and a memory controller and an access method thereof are provided. The memory storage device includes a rewritable non-volatile memory chip having a plurality of physical blocks. The access method includes configuring a plurality of logical blocks to be mapped to a part of the physical blocks and dividing the logical blocks into at least a first partition and a second partition, wherein the first partition records an auto-execute file. The access method also includes determining whether a trigger signal is existent and sending a media ready message to a host system if the trigger signal is existent, so as to allow the host system to automatically run the auto-execute file and receive a first password. The access method further includes determining whether to provide the logical blocks in the second partition to the host system according to the first password received from the host system.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: December 6, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chia-Jung Hsu, Shih-Hsien Hsu
  • Patent number: 9507536
    Abstract: Dynamically allocates a new target volume and a Flashcopy map (fcmap) for ingest upon one of a mount operation and a clone operation breaking a FlashCopy chain for creating a stable FlashCopy Map (fcmaps) for ingest while a Flashcopy backup is mounted.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay H. Akirav, Joseph W. Dain, Gregory T. Kishi, Osnat Shasha
  • Patent number: 9507530
    Abstract: A method of operating a memory system includes; storing data in a buffer region of the nonvolatile memory, later issuing a migration request directed to the data stored in the buffer region and executing a migration operation to move the data from buffer region to a main region of the nonvolatile memory device. Upon completion of the migration operation, marking a migration operation completion time, and after an initial verify shift (IVS) time has elapsed following the migration operation completion time, updating a mapping table associated with the data in view of the executed migration operation.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Young Seo, Young Bong Kim, Dongeun Shin
  • Patent number: 9501238
    Abstract: A method of managing a memory by an electronic device is provided. The method includes configuring a swap data amount per unit time, identifying an actual use amount of swap data, and comparing the identified actual use amount of the swap data with the configured swap data amount per unit time.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunghwan Yun, Seijin Kim
  • Patent number: 9501232
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9501423
    Abstract: A program execution device includes a program loader reading a machine language program including a machine language code and access frequency information; an address conversion table creator creating an address conversion table including entries, each of which indicates a relation between a logical address range and a physical address range; and a TLB register registering, in a TLB, an entry of the address conversion table storing a logical address range accessed according to the machine language code. When determining that the frequency of access to a logical address range is high based on the access frequency information, the address conversion table creator adjusts the size of an entry storing this logical address range to an appropriate size.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: November 22, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Yoshitaka Nishida
  • Patent number: 9495253
    Abstract: The present disclosure relates generally to a method and system for creating, replicating, and providing access to virtual snapshots of a disk storage block of a disk storage system or subsystem. In one embodiment, the present disclosure relates to a virtual snapshot accessible to local users of a local data storage device. The virtual snapshot may direct local users to a snapshot stored on computer-readable storage medium at a remote data storage site, but give the appearance as if data of the corresponding snapshot is stored locally. The virtual snapshot is replaced by replication of the snapshot from the remote data storage site to the local data storage device. Each snapshot may relate to data of a logical data volume, the logical data volume being an abstraction of data blocks from one or more physical storage devices.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: November 15, 2016
    Assignee: Dell International L.L.C.
    Inventors: Michael H. Pittelko, Mark David Olson
  • Patent number: 9495108
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9489144
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9489142
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9478263
    Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 25, 2016
    Assignee: APPLE INC.
    Inventors: Bin Ni, Kai Lun Charles Hsiung, Yanzhe Liu, Sukalpa Biswas