Abstract: A RAID controller includes a cache memory in which write cache blocks (WCBs) are protected by a RAID-5 (striping plus parity) scheme while read cache blocks (RCBs) are not protected in such a manner. If a received cache block is an RCB, the RAID controller stores it in the cache memory without storing any corresponding parity information. When a sufficient number of WCBs to constitute a full stripe have been received but not yet stored in the cache memory, the RAID controller computes a corresponding parity block and stores the RCBs and parity block in the cache memory as a single stripe.

Abstract: A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.

Abstract: An information processing system and computer program storage product for managing objects stored in a shared memory cache. The system includes at least a plurality of cache readers accessing data from the shared memory cache. The system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.

Abstract: A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.

Abstract: A method of allocating data to a storage block included in a storage network may include determining a plurality of characteristics associated with a storage block included in a storage network. The plurality of characteristics may include storage capacity of the storage block, available storage space of the storage block, likelihood of loss of data stored on the storage block, availability of the storage block with respect to the storage network, and use of the storage block. The method may further include allocating data to the storage block based on the plurality of characteristics.

Abstract: A method for managing objects stored in a shared memory cache. The method includes accessing data from the shared memory cache using at least a plurality of cache readers. A system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.

Abstract: An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.

Abstract: A determining unit selects one storage device each from storage devices of an external storage apparatus and storage devices of a storage apparatus to which the determining unit belongs. At this point, based on a copy request, the determining unit preferentially selects, within each of the external storage apparatus and the storage apparatus, a storage device including a larger number of logical volumes (LVs) which belong to copy unexecuted LV pairs compared to other storage devices therein. Further, the determining unit determines, as a copy execution target, a copy unexecuted LV pair in which a LV provided in one of the selected two storage devices is a copy source and a LV provided in the other storage device is a copy destination. A copy unit copies data stored in the copy source LV, which belongs to the determined LV pair, to the copy destination LV of the LV pair.

Abstract: Machine implemented method and system are provided. A processor for a computing device allocates an address range with an address to write to an intermediate storage location. The processor configures a device communicating with the computing device for writing information at the intermediate storage location and at a plurality of storage locations. The computing device sends the address for the intermediate storage location with data that needs to be written at one of the plurality of storage locations with an identifier identifying the one of the plurality of storage locations; and the device first writes the data at the intermediate storage location and then updates the one of the plurality of storage locations identified by the identifier.

Abstract: Data is collected by an active node from passive nodes and arranges and stores the collected data on receiving nodes. A source node extracts the data format, and a remote memory blade identification (ID), a remote memory blade address, and ranges of the RMMA space, and composes and sends metadata to the receiving nodes and receiving racks.

Abstract: A computational device receives a request to copy a source logical block of a thin provisioned source logical unit to a target logical block of a thin provisioned target logical unit, wherein in thin provisioned logical units physical storage space is allocated in response to a write operation being performed but not during creation of the thin provisioned logical units. The computational device generates metadata that stores a correspondence between the source logical block and the target logical block, while avoiding allocating any physical storage space for the target logical block in the thin provisioned target logical unit.

Abstract: Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate.

Abstract: A device may comprise a plurality of non-volatile memories configured to store a plurality of physical pages and a controller coupled thereto, configured to program and read data to and from the plurality of non-volatile memory devices. The data may be stored in a plurality of logical pages (L-Pages) of non-zero length at starting addresses within the plurality of physical pages and execute first and second commands to indicate that first and second physical locations within the plurality of non-volatile memory devices no longer contains valid data and are now free space. This may be done by carrying out first and second virtual write operations of first and second L-Pages of a predetermined length at first and second unique addresses within a virtual address range that does not correspond to any of the physical pages, and accounting for an amount of free space gained as a result of executing the commands.

Abstract: Techniques for implementing a data queuing and/or caching scheme for optimizing data storage are described herein. Data write requests are received and processed by at least queuing the requests and/or associated data for recording upon one or more data storage devices. The order within the queue, as well as the order in which the queued requests are serviced, may, in some embodiments, be optimized. The stored data are verified by determining the position of a write pointer implemented by the one or more data storage devices relative to the contents and/or position of the queued data requests.

Abstract: A cache module leverages a logical address space and storage metadata of a storage module (e.g., virtual storage module) to cache data of a backing store. The cache module maintains access metadata to track access characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not currently in the cache. The access metadata may be separate from the storage metadata maintained by the storage module. The cache module may calculate a performance metric of the cache based on profiling metadata, which may include portions of the access metadata. The cache module may determine predictive performance metrics of different cache configurations. An optimal cache configuration may be identified based on the predictive performance metrics.

Abstract: A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern.

Abstract: A plurality of data arrays are coupled to a plurality of nodes via a plurality of adapters. The plurality of adapters discover the plurality of data arrays during startup, and information about the plurality of data arrays are communicated to corresponding local nodes of the plurality of nodes, wherein the local nodes broadcast the information to other nodes of plurality of nodes. A director node of the plurality of nodes determines which data arrays of the plurality of data arrays are a current set of global metadata arrays, based on the broadcasted information.

Abstract: A method of ensuring that serialization is maintained between separate transactions while searching and/or modifying a variable length queue includes searching a queue using a transaction. A first sequence number is retrieved from a queue header and a second sequence number is retrieved from local storage for the transaction. The first sequence number is compared with the second sequence number according to embodiments. The search of the queue is resumed using an address of a next element saved from a previous transaction responsive to the first sequence number matching the second sequence number. The search of the queue is restarted at a first element responsive to the first sequence number not matching the second sequence number.

Abstract: A system for ensuring that serialization is maintained between separate transactions while searching and/or modifying a variable length queue is system includes a computer processor and logic executable by the computer processor. The logic is configured to implement a method. The method includes searching, by a processing device, a queue using a transaction. A first sequence number is retrieved from a queue header and a second sequence number is retrieved from local storage for the transaction. The first sequence number is compared with the second sequence number according to embodiments. The search of the queue is resumed using an address of a next element saved from a previous transaction responsive to the first sequence number matching the second sequence number. The search of the queue is restarted at a first element responsive to the first sequence number not matching the second sequence number.

Abstract: An erasure system and method for sorting, tracking, and erasing a plurality of data storage devices using enterprise hardware and software designed for data storage. The erasure system may include a server, drive arrays having receptacles for communicably coupling with the data storage devices, and a drive array controller configured for communicably coupling the server with the drive arrays. The server may receive specification information regarding each of the drive arrays and each of the data storage devices in the receptacles of the drive arrays for erasure and logging purposes. Then the server may overwrite each of the data storage devices according to the DoD 5220.22-M standard, thereby erasing the data storage devices. The server may also create log files corresponding to each of the data storage devices, including information like time, date, and if the erasure of the data storage device is complete or has failed.