Patents Examined by Reginald G. Bragdon
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Patent number: 11977482Abstract: To avoid hash table collisions, such as in response to sequential addresses, a hash module is provided that includes a first multiplexer that, responsive to a control signal, outputs received data on one of two or more scramblers. The scramblers are configured to selectively receive the selected data output from the first multiplexer and perform a scrambler operation on the selected data to generate scrambled data. A second multiplexer outputs the scrambled data to a first hash module configured to performs a hash function on the scrambled data to generate a hash value. A second hash module, responsive to a collision occurring in the first hash module, perform a hash function on the scrambled data received from the first hash module. The use of a scrambler reduces collisions in the hash module outputs over time and multiple scramblers may be used to further reduce collisions.Type: GrantFiled: September 2, 2021Date of Patent: May 7, 2024Assignee: FLC Technology Group, Inc.Inventors: Rong Xu, Xiaojue Zeng, Fan Yang, Hunglin Hsu, Sehat Sutardja
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Patent number: 11972131Abstract: An online takeover method for a heterogeneous storage volume, including: executing a service: a host executing upper layer service data access by means of a second volume label of a storage volume of a second storage; generating a volume label: a first storage taking over the storage volume of the second storage and generating a first volume label for the storage volume that has been taken over; flushing data: flushing host side cache data corresponding to the storage volume of the second storage to the storage volume of the second storage; changing a directory: changing directory information of an upper layer service running on the host; and storage migration: when the directory information of the upper layer service has been changed, migrating data of the storage volume to the first storage.Type: GrantFiled: November 30, 2021Date of Patent: April 30, 2024Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.Inventor: Xianning Sun
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Patent number: 11966631Abstract: A method and system for maintaining command queue order are disclosed. According to certain embodiments, commands are read from a host, storing command queue IDs in an array that will keep the queue IDs in order. After having the queue IDs stored in the array, the commands are processed in the data storage device (DSD). After processing, the commands are provided to a completion order adjustment module that will order the commands in queue ID order for sequential commands to be returned to the host. In certain embodiments, for a sequential command, other commands of the same sequence are searched for the array and ordered with the sequential command. If a particular command of the sequence is not found, the completion order adjustment module will wait to transfer the sequence until each command of the sequence is found. For commands not part of a sequence, these commands are transferred to the host.Type: GrantFiled: April 16, 2021Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Sang Yun Jung, Min Woo Lee, Min Young Kim
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Patent number: 11966638Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically generate Redundant Array of Independent Nodes (RAIN) parity information for zone-based memory allocations. The RAIN parity information is generated for a given zone or set of zones on the basis of whether the given zone or set of zones satisfy a zone completeness criterion. The zone completeness criterion can represent a specified size such that when a given zone reaches the specified size, the parity information for that zone is generated.Type: GrantFiled: April 13, 2022Date of Patent: April 23, 2024Assignee: Micron Technology, Inc.Inventor: Luca Bert
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Patent number: 11966618Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device is arranged into at least a first super device and a second super device, each of the super devices having a plurality of active zones. The controller is configured to determine that each of the super devices includes both cold zones and hot zones, where a cold zone is a zone that is overwritten less than a hot zone. The controller is further configured to move cold zones from one super device to another super device upon determining that the another super device is below a threshold limit, where the threshold limit is a minimum free space to be maintained in a super device. The controller is further configured to move cold zones between super devices, such that the cold zones are concentrated in at least one super device.Type: GrantFiled: August 25, 2021Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ravishankar Surianarayanan, Matias Bjorling
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Patent number: 11968843Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.Type: GrantFiled: February 7, 2019Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
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Patent number: 11960753Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device includes at least a first super device and a second super device. Each of the super devices includes a plurality of active zones and a threshold value for a number of cold zones. The controller classifies zones as either a cold zone or hot zone depending the number of resets to the zone. If the number of resets to the zone is greater than a threshold reset value, then the zone is classified as a hot zone, otherwise the zone is classified as a cold zone. The controller is configured to determine that the number of cold zones is greater than the threshold value for a super device and move data from at least one cold zone from the super device to a zone of another super device.Type: GrantFiled: August 25, 2021Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ravishankar Surianarayanan, Matias Bjorling
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Patent number: 11960735Abstract: The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.Type: GrantFiled: September 1, 2021Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventor: David G. Springberg
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Patent number: 11954028Abstract: There is disclosed a method of storing an encoded block of data in memory comprising encoding a block of data elements and determining a memory location (26) at which the encoded block of data is to be stored. The memory location (26) at which the encoded block of data is stored is then indicated in a header (406) for the encoded block of data by including in the header a memory address value (407) together with a modifier value (500) representing a modifier that is to be applied to the memory address value (407) when determining the memory location (26). When the encoded block of data is to be retrieved, the header (406) is read and processed to determine the memory location (26).Type: GrantFiled: March 31, 2022Date of Patent: April 9, 2024Assignee: Arm LimitedInventors: Edvard Fielding, Jian Wang, Jakob Axel Fries, Carmelo Giliberto
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Patent number: 11954353Abstract: In an approach to improve magnetic tape file systems through tape-to-tape copying between nodes on a Linear Tape File System using a cluster-wide named pipe. Embodiments transfer data between a first node and a second node. Additionally, both the first node and the second node implement a parallel shared-disk file system through a data path for node data reading and writing from a shared-disk and to the shared-disk. Further, to transfer data between the first node and the second node, embodiments, write, by the first node, the data for tape-to-tape copy from a first tape drive to the shared-disk, and write, by the second node, the data written from the shared-disk to a second tape drive.Type: GrantFiled: September 24, 2021Date of Patent: April 9, 2024Assignee: International Business Machines CorporationInventors: Atsushi Abe, Tohru Hasegawa, Hiroshi Itagaki, Tsuyoshi Miyamura, Shinsuke Mitsuma, Noriko Yamamoto
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Patent number: 11954346Abstract: A method is provided for use in a storage processor, the method comprising: receiving a write request, the write request including a request to store user data in an array that includes a plurality of solid-state drives (SSD); executing the write request by: identifying metadata that is associated with the write request, and writing the user data and the metadata to different data streams that are opened on the plurality of SSDs; wherein writing the user data and the metadata to different data streams causes: (i) the user data to be stored in one or more first erase units of any of the plurality of SSDs, and (ii) the metadata to be stored in one or more second erase units of any of the plurality of SSDs, such that no part of the metadata is stored on any of the one or more first erase units, and no part of the user data is stored on any of the one or more second erase units.Type: GrantFiled: April 23, 2021Date of Patent: April 9, 2024Assignee: EMC IP Holding Company LLCInventors: Amitai Alkalay, Lior Kamran, Steven Morley
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Patent number: 11922048Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.Type: GrantFiled: January 13, 2021Date of Patent: March 5, 2024Assignee: SK hynix Inc.Inventors: Hye Mi Kang, Eu Joon Byun
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Patent number: 11907132Abstract: A method for managing designated authority status in a cache line includes identifying an initial designated authority (DA) member cache for a cache line, transferring DA status from the initial DA member cache to a new DA member cache, determining whether the new DA member cache is active, indicating a final state of the initial DA cache responsive to determining that the new DA member cache is active, and overriding a DA state in a cache control structure in a directory. A method for managing cache accesses during a designated authority transfer includes receiving a designated authority (DA) status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache's copy of the cache line until invalidation by the first cache is complete.Type: GrantFiled: March 23, 2022Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Jason D Kohl, Gregory William Alexander, Timothy Bronson, Akash V. Giri, Winston Herring
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Patent number: 11907118Abstract: Method, systems and apparatuses may provide for technology that identifies first data and second data to be stored in a data storage. Each of the first data and the second data are in a first data format. Some technology may also interleave the first data with the second data. The interleaved first and second data are in a second data format. The second data format is different from the first data format.Type: GrantFiled: November 7, 2019Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Yong Wu, Mohammad Haghighat, Zhong Cao, Feng Yuan, Hongzhen Liu
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Patent number: 11907119Abstract: Methods, systems, and devices for array access with receiver masking are described. A first device may issue to a second device a first sequence of write commands for a set of data. The first sequence of write commands may indicate different memory addresses in an order. After issuing the first sequence of write commands, the first device may issue to the second device a second sequence of read commands for the set of data. The second sequence of read commands may indicate the different memory addresses in the same order as the first sequence of write commands. Based on issuing the second sequence of read commands, the first device may receive the set of data from the second device.Type: GrantFiled: July 14, 2021Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Natalija Jovanovic, Andrea Sorrentino, Marcos Alvarez Gonzalez
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Patent number: 11893254Abstract: A method, a computer program product, and a system of dynamically managing permissions of storage blocks. The method includes predicting at least one storage block that will be accessed by a user on a storage device and predicting a time window when the storage block will be accessed the user. The predictions can be performed by a machine learning model trained using the historical accesses and access times of the user. The method also includes granting the user an access to the storage block during the time window and monitoring whether the storage block is accessed by the user. The method also includes determining, based on the monitoring, that the user accessed the storage block, and revoking the access to the storage block granted to the user after a predetermined access time.Type: GrantFiled: June 4, 2021Date of Patent: February 6, 2024Assignee: International Business Machines CorporationInventors: Saritha Arunkumar, Kuntal Dey, Seema Nagar, Kartik Srinivasan, Anjali Tibrewal
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Patent number: 11836514Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may receive a request for a secure memory region with fault resiliency from first processor instructions being executed at a first processor privilege level; allocate a first enclave, in which the first enclave protects at least one of second processor instructions and data from being read by and from being altered by third processor instructions executing at a second processor privilege level; allocate a second enclave, in which the second enclave protects the at least one of the second processor instructions and the data from being read by and from being altered by the second processor instructions; store the at least one of the second processor instructions and the data in the first enclave; and mirror the at least one of the second processor instructions and the data in the second enclave.Type: GrantFiled: January 19, 2021Date of Patent: December 5, 2023Assignee: Dell Products L.P.Inventors: Vinod Parackal Saby, Krishnaprasad Koladi, Gobind Vijayakumar
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Patent number: 11816346Abstract: A data migration orchestration system includes a data migration orchestration engine, a user interface, and an orchestration configuration database. The user interface provides a menu-based system configured to guide a user through a process of implementing a data migration instance. The orchestration configuration database contains information about the types of data migration technologies available to be used to implement data migration operations between disparate storage systems.Type: GrantFiled: September 29, 2021Date of Patent: November 14, 2023Assignee: Dell Products, L.P.Inventors: Vijesh Shetty, Sivashankari Chandrasekaran
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Patent number: 11816344Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages at least one storage area that is obtained by logically dividing a storage space of the nonvolatile memory. One or more storage areas in the at least one storage area store one or more data pieces, respectively. The controller manages first information on one or more times in which integrity of the one or more data pieces have been confirmed last, respectively.Type: GrantFiled: September 8, 2021Date of Patent: November 14, 2023Assignee: Kioxia CorporationInventor: Naoki Esaka
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Patent number: 11797228Abstract: A data storage device including, in one implementation, a non-volatile memory device having a memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. An activity level of the data storage device is monitored to determine whether the data storage device is in an idle condition based on the monitored activity level. Background operations are performed in response to the data storage device being determined to be in an idle condition Relocation operations are then performed in response to determining that the data storage device remains in the idle condition, wherein the relocation operations are executed in an order based on a priority level associated with each of the relocation operations.Type: GrantFiled: June 24, 2021Date of Patent: October 24, 2023Assignee: Western Digital Technologies, Inc.Inventors: Sridhar Prudviraj Gunda, Yarriswamy Chandranna