Patents Examined by Reginald G. Bragdon
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Patent number: 12197782Abstract: A storage command is received from a client computer. The storage command includes a key associated with a content object that is to be written to two or more storage nodes in response to the command. A virtual address space is used to indicate a storage location of the content object. A virtual address of the virtual address space is assigned to the content object. The content object is redundantly stored the two or more storage nodes at respective two or more device addresses of the respective two or more storage nodes. The two or more device addresses are mapped to the virtual address, and the virtual address is returned to the client computer as a hint.Type: GrantFiled: February 18, 2022Date of Patent: January 14, 2025Assignee: Seagate Technology LLCInventors: Shankar Tukaram More, Vidyadhar Charudatt Pinglikar
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Patent number: 12189977Abstract: A storage device is disclosed. The storage device may include a host interface to receive a write request from a host, the write request may include a data and a logical address of the data. The storage device may further include a first storage for the data. The storage device may further include a retention period determiner to determine a retention period for the data. The storage device may further include a translation layer to select a physical address in the first storage to store the data based at least in part on the retention period. The storage device may further include a second storage for a logical-to-physical mapping table to map the logical address to the physical address and the retention period. Finally, the storage device may include a controller to program the data into the physical address in the first storage.Type: GrantFiled: July 1, 2021Date of Patent: January 7, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ramdas P. Kachare, Dongwan Zhao
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Patent number: 12175113Abstract: In techniques for flushing data, based on a maturity level of a storage segment, the storage segment is inserted into a list to be flushed corresponding to the maturity level in a plurality of lists to be flushed, the plurality of lists to be flushed respectively correspond to different maturity levels, and the maturity level at least indicates a proportion of the number of data-written blocks to the total number of blocks of the storage segment; and the list to be flushed for the corresponding maturity level in the plurality of lists to be flushed is flushed to a disk array according to a descending order of the maturity levels. In this way, the bandwidth utilization of the disk array can be improved.Type: GrantFiled: May 25, 2022Date of Patent: December 24, 2024Assignee: Dell Products L.P.Inventors: Qiaosheng Zhou, Ming Zhang, Chen Gong
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Patent number: 12175091Abstract: Supporting a stateless controller in a storage system, including: sending, from a storage system controller to a storage device, a request for one or more locations of control information for the storage device, the storage system controller being external to the storage device; receiving, from the storage device, the one or more locations of one or more memory blocks that include the control information; and retrieving, from the storage device, the control information from the one or more memory blocks.Type: GrantFiled: June 21, 2022Date of Patent: December 24, 2024Assignee: PURE STORAGE, INC.Inventor: Eric D. Seppanen
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Patent number: 12159053Abstract: A memory authentication system initiates various memory operations on a memory chip and then assesses the performance of the memory chip in performing such operations in an attempt to identify a signature in the chip's performance that can be used to identify the chip's source. As an example, a partial erase operation may be performed on programmed memory cells in order to drain some charge from the cells but allowing some charge to remain in the cells. Due to process variations during manufacturing, charge should drain from the cells at different rates such that some of the cells may flip to an erase state while other cells remain in a program state. The pattern of bit flips defines a unique signature that may be used to identify the chip's manufacturing source (e.g., the foundry at which the chip was manufactured).Type: GrantFiled: July 29, 2022Date of Patent: December 3, 2024Assignee: Board of Trustees for the University of Alabama, for and on behalf of the University of Alabama in HuntsvilleInventors: Biswajit Ray, Aleksandar Milenkovic
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Patent number: 12131063Abstract: Methods and apparatus offload tiered memories management. The method includes obtaining a pointer to a stored memory management structure associated with tiered memories, where the memory management structure includes a plurality of memory management entries and each memory management entry of the plurality of memory management entries includes information for a memory section in one of the tiered memories. In some instances, the method includes scanning at least a part of the plurality of memory management entries. In certain instances, the method includes generating a memory profile list, where the memory profile list includes a plurality of profile entries and each profile entry of the plurality of profile entries corresponding to a scanned memory management entry in the memory management structure.Type: GrantFiled: March 31, 2021Date of Patent: October 29, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Kevin M. Lepak
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Patent number: 12124710Abstract: A method of writing data to a protected region in response to a request from a host includes receiving a first write request including a first host message authentication code and a first random number from the host, verifying the first write request based on a write count, the first random number, and the first host message authentication code, updating the write count based on a result of verifying the first write request, generating a first device message authentication code based on the updated write count and the first random number, and providing the host with a first response including the first device message authentication code and a result of the verifying of the first write request.Type: GrantFiled: July 3, 2023Date of Patent: October 22, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyunsook Hong, Jisoo Kim, Yongsuk Lee, Younsung Chu, Hyungsup Kim
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Patent number: 12118226Abstract: A method of shuffling data may include shuffling a first batch of data using a first memory on a first level of a memory hierarchy to generate a first batch of shuffled data, shuffling a second batch of data using the first memory to generate a second batch of shuffled data, and storing the first batch of shuffled data and the second batch of shuffled data in a second memory on a second level of the memory hierarchy. The method may further include merging the first batch of shuffled data and the second batch of shuffled data. A data shuffling device may include a buffer memory configured to stream one or more records to a partitioning circuit and transfer, by random access, one or more records to a grouping circuit.Type: GrantFiled: April 7, 2021Date of Patent: October 15, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chen Zou, Hui Zhang, Joo Hwan Lee, Yang Seok Ki
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Patent number: 12105980Abstract: A tool for tape library hierarchical storage management. The tool determines there is available tape capacity on a tape cartridge mounted to a tape drive to migrate data from a migration queue during recall operations. The tool sends a locate end of data (EOD) command to the tape drive. The tool determines the migration queue is within a longitudinal position (LPOS) range. The tool writes data from the migration queue to the tape cartridge within the LPOS range.Type: GrantFiled: September 29, 2023Date of Patent: October 1, 2024Assignee: International Business Machines CorporationInventors: Noriko Yamamoto, Hiroshi Itagaki, Tsuyoshi Miyamura, Tohru Hasegawa, Shinsuke Mitsuma, Atsushi Abe
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Patent number: 12105988Abstract: A memory system may include a memory device including a plurality of memory blocks, a buffer memory device, and a memory controller. The buffer memory device includes a read buffer configured to store the data read from the memory device and a keep buffer configured to store part of the read data. The memory controller operates to identify keeping data among data stored in the read buffer according to a number of error bits in the keeping data when it was read from the memory device, store the keeping data in the keep buffer, and remove the keeping data from the read buffer. The memory controller may store the keeping data in any one of the plurality of memory blocks based on information related to the keeping data.Type: GrantFiled: December 14, 2021Date of Patent: October 1, 2024Assignee: SK hynix Inc.Inventor: Jong Min Lee
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Patent number: 12099839Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.Type: GrantFiled: May 7, 2021Date of Patent: September 24, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yuhwan Ro, Shinhaeng Kang, Seongil O, Seungwoo Seo
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Patent number: 12093537Abstract: A data storage device stores files in its memory. The files may be logically fragmented in that various parts of a given file may be located in non-continuous logical addresses, which can be disadvantageous. The host can send a request to the data storage device to reduce such logical fragmentation. For example, the host can send a swap command to the data storage device, in response to which the data storage device swaps the logical addresses of data fragments of two different files. This results in the logical address of one or both of the data fragments being continuous with the logical address of another data fragment of the same file. This logical address swap can take place without physically moving the data in the memory.Type: GrantFiled: July 11, 2023Date of Patent: September 17, 2024Assignee: Sandisk Technologies, Inc.Inventors: Daniel J. Linnen, Ramanathan Muthiah, Judah Gamliel Hahn
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Patent number: 12079140Abstract: Systems, apparatuses, and methods for performing efficient translation lookaside buffer (TLB) invalidation operations for splintered pages are described. When a TLB receives an invalidation request for a specified translation context, and the invalidation request maps to an entry with a relatively large page size, the TLB does not know if there are multiple translation entries stored in the TLB for smaller splintered pages of the relatively large page. The TLB tracks whether or not splintered pages for each translation context have been installed. If a TLB invalidate (TLBI) request is received, and splintered pages have not been installed, no searches are needed for splintered pages. To refresh the sticky bits, whenever a full TLB search is performed, the TLB rescans for splintered pages for other translation contexts. If no splintered pages are found, the sticky bit can be cleared and the number of full TLBI searches is reduced.Type: GrantFiled: March 24, 2023Date of Patent: September 3, 2024Assignee: Apple Inc.Inventors: John D. Pape, Brian R. Mestan, Peter G. Soderquist
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Patent number: 12073109Abstract: The system allocates, in a distributed system comprising a plurality of nodes, a plurality of portions of memory which comprise shared remote memory content. The system registers the allocated portions with an operating system to be accessed via RDMA. The system accesses, by a first node, the allocated portions to obtain a local copy. The system performs an atomic operation on one or more bits of the shared remote memory content via libfabric atomic application programming interface calls, by one or more of: updating the one or more bits based on a new value and an offset; retrieving, from the shared remote memory content based on the offset, a current value of the one or more bits prior to the updating; and performing an action on the shared remote memory content based on a comparison of the retrieved current value with an expected value in the local copy.Type: GrantFiled: June 29, 2021Date of Patent: August 27, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Oleg Neverovitch, Yann Livis, Dmitry L. Ivanov
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Patent number: 12073114Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.Type: GrantFiled: September 30, 2021Date of Patent: August 27, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Hideki Kanayama, Eric M. Scott
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Patent number: 12067288Abstract: The present invention provides a storage device including a controller and methods for operating the storage device and the controller. A controller of a storage device may comprise: an interface controller; a memory controller; a processor configured to transmit downstream commands and upstream commands to the memory controller. The memory controller may be coupled between the interface controller and the processor and may comprise: a first command queue; a second command queue; and a racing handler.Type: GrantFiled: November 23, 2021Date of Patent: August 20, 2024Assignee: SILICON MOTION INC.Inventors: Che Jen Su, Bao Ren Guo
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Patent number: 12066952Abstract: Provided is a data processing method, which includes: in response to a logical volume receiving a write request, whether a logical address carried in the write request is occupied by a data unit in the logical volume is determined; if not, a data grain which is closest to the size of a data block and is greater than the size of the data block is determined; a new data unit is created in the logical volume by use of the logical address as an initial address and by use of the closest data grain as the length, and a logical address range occupied by the data block in the new data unit is recorded; the data block is written into an underlying storage and a written physical address is returned; and a mapping relationship between the initial address and the physical address is established and saved.Type: GrantFiled: October 29, 2021Date of Patent: August 20, 2024Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.Inventor: Yazhou Gang
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Patent number: 12061819Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.Type: GrantFiled: December 6, 2021Date of Patent: August 13, 2024Assignee: Micron Technology, Inc.Inventors: Nitul Gohain, Jameer Mulani, Jotiba Koparde
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Patent number: 12045482Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.Type: GrantFiled: July 29, 2022Date of Patent: July 23, 2024Assignee: Micron Technology, Inc.Inventors: Wai Leong Chin, Francis Chee Khai Chew, Trismardawi Tanadi, Chun Sum Yeung, Lawrence Dumalag, Ekamdeep Singh
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Patent number: 12019555Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.Type: GrantFiled: June 9, 2022Date of Patent: June 25, 2024Assignee: Micron Technology, Inc.Inventor: Steven Jeffrey Wallach