Patents Examined by Reginald G. Bragdon
  • Patent number: 11079945
    Abstract: A processing system includes a memory controller coupleable to a RAM, and a ROM configured to store boot information that includes default values for a set of one or more memory timing parameters. At least one processor is configured to, during initialization, configure the memory controller to utilize the default values for the set of one or more memory timing parameters. The at least one processor further is configured to, during operation of the processing system following initialization, receive user input representing one or more updated values for one or more corresponding memory timing parameters of the set, and to dynamically reconfigure the memory controller to utilize one or more updated values for the set of one or more memory timing parameters for the signaling. The processing system further is configured to conduct one or more memory access operations for the RAM using the reconfigured memory controller.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 3, 2021
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Omer Irshad, Joohyun Lee
  • Patent number: 11080203
    Abstract: High performance data storage device is disclosed, which has a memory controller dynamically updating mapping information on the temporary storage to manage physical space information mapped to a logical address recognized by a host. The memory controller uses a first bit to an Nth bit of the physical space information to indicate a physical space of the non-volatile memory or a cache address of the data cache space, without using additional bits to map the physical space information to the non-volatile memory or the data cache space, where N is a number greater than one. Among numbers formed by the first to the Nth bit, the memory controller uses numbers corresponding to non-existent physical space of the non-volatile memory to map the physical space information to the non-volatile memory or the data cache space.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 3, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Yang-Chih Shen, Shih-Chang Chang
  • Patent number: 11074169
    Abstract: The present disclosure includes apparatuses, electronic device readable media, and methods for memory controlled data movement and timing. A number of electronic device readable media can store instructions executable by an electronic device to provide programmable control of data movement operations within a memory. The memory can provide timing control, independent of any associated processor, for interaction between the memory and the associated processor.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 11074007
    Abstract: A system having a processing device and a controller, operatively connected to a memory sub-system via a communication channel, to: store information identifying an amount of available capacity of a buffer of the memory sub-system; transmit, through the communication channel to the memory sub-system, one or more write commands to store data in memory components of the memory sub-system, where the memory sub-system queues the one or more write commands in the buffer; update the information by deducting, from the amount of available capacity, an amount of buffer capacity used by the one or more write commands to generate a current amount of available capacity of the buffer; and determine whether to generate an information request to the memory sub-system based at least in part on the current amount of available capacity.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Trevor Conrad Meyerowitz, Dhawal Bavishi
  • Patent number: 11073996
    Abstract: During preparation for migration of a logical volume from a source data storage appliance to a destination data storage appliance, a determination is made as to whether at least one host that accesses a copy of the logical volume contained in the source data storage appliance is managed by a host administration server. In response to determining that at least one host that accesses the copy of the logical volume contained in the source data storage appliance is managed by the administration server, a rescan request is transmitted to the administration server. The rescan request causes the host administration server to instruct each host that is managed by the host administration server that accesses the copy of the logical volume contained in the source data storage appliance to perform a rescan operation to discover at least one new path to the logical volume.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: July 27, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Dmitry Tylik, Michael Zeldich, Vinod K. Rajasekaran, Anil K. Koluguri
  • Patent number: 11068388
    Abstract: A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Brent S. Haukness
  • Patent number: 11068192
    Abstract: Aspects relate to techniques for using read-only volume replicas in a distributed computing environment to enable over-subscription on server performance. In order to provide a good customer experience, the I/O handling replicas of a volume are typically reserved at a high percentage of the customer's desired performance. A read-only replica of the volume does not serve user I/O, and can therefore be reserved at a much lower percentage of desired performance. Particularly, as the number of read-only replicas increases, the performance reservation can be lowered due to the statistical likelihood that the server(s) hosting at least one read-only replica will have sufficient performance to support the desired reads during new volume creation (even though that performance has not been fully reserved). Aspects relate to techniques for selecting among read-only replicas to serve reads during creation of a new volume copy.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Magee Greenwood, James Michael Thompson, Igor A. Kostic
  • Patent number: 11068181
    Abstract: A data storage system in which a transaction is generated that indicates at least one data block of a logical volume to be written to non-volatile data storage of a data, and in which the logical volume is accessible to multiple nodes in the data storage system. A system-wide lock is obtained for each data block indicated by the transaction. A new generation identifier is then created that is equal to a last transaction identifier that was created and stored during processing of a previously completed transaction. Each data block indicated by the transaction is stored into the non-volatile data storage of the data storage system together with the new generation identifier and the last transaction identifier is updated before each system-wide lock on each data block indicated by the transaction is released.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 20, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vamsi K. Vankamamidi, Socheavy Heng, Philippe Armangau, Christopher A. Seibel, James McCoy
  • Patent number: 11061578
    Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Fulvio Rori, Jung Sheng Hoei
  • Patent number: 11048430
    Abstract: Techniques are provided for object store mirroring. Data within a storage tier of a node may be determined as being data to tier out to a primary object store based upon a property of the data. A first object is generated to comprise the data. A second object is generated to comprise the data. The first object is transmitted to the primary data store for storage in parallel with the second object being transmitted to a mirror object store for storage. Tiering of the data is designated as successful once acknowledgements are received from both the primary object that the first object was stored and the mirror object store that the second object was stored.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 29, 2021
    Assignee: NetApp, Inc.
    Inventors: Anil Paul Thoppil, Cheryl Marie Thompson, Qinghua Zheng, Jeevan Hunsur Eswara, Nicholas Gerald Zehender, Ronak Girishbhai Ghadiya, Sridevi Jantli
  • Patent number: 11048447
    Abstract: Embodiments for providing direct access to non-volatile memory by a processor. One or more accelerators may be provided, via an application programming interface (“API”), direct access to non-volatile storage independent of a host central processing unit (“CPU”) on a control path or data path to perform a read operation and write operation of data.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zaid Qureshi, I-Hsin Chung, Wen-Mei Hwu, Jinjun Xiong
  • Patent number: 11048636
    Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11042490
    Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Donald M. Morgan, Sean S. Eilert, Bryce D. Cook
  • Patent number: 11042324
    Abstract: A technique is directed to managing a redundant array of independent disks (RAID) group. The technique involves forming the RAID group from storage devices of different types that provide different data storage characteristics. The technique further involves receiving input/output (I/O) requests, and performing I/O operations on the RAID group in response to the I/O requests.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 22, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Anton Kucherov, Ronen Gazit, Uri Shabi
  • Patent number: 11042319
    Abstract: A method is used in detecting slow storage device operations in a storage system. Information regarding a set of storage device operations performed on a storage device in the storage system is monitored in real time. The information is analyzed in real time. A determination is made from the analysis whether the storage device can be identified as a slow storage device. At least one action is performed on the storage system, while the storage system continues to operate, to isolate the slow storage device.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 22, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Shuo Lv, Wenjun Wang
  • Patent number: 11042317
    Abstract: A memory system includes a memory device including a first memory block and a second memory block; and a controller suitable for controlling the memory device, wherein the controller includes a sequential index calculator suitable for calculating a sequential index based on first logical block address (LBA) information and second LBA information that are written in the first memory block; an internal operation determining component suitable for determining whether an internal operation is to be performed on the first memory block, by comparing the sequential index of the first memory block with a threshold value; and an internal operation performing component suitable for migrating pieces of LBA information stored in the first memory block to the second memory block to rearrange the pieces of LBA information, when it is determined that the internal operation is to be performed on the first memory block.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 22, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11042300
    Abstract: In an example, a method of processing commands for a non-volatile storage device includes storing the commands among a plurality of first-level queues in a random access memory (RAM). Each command is assigned to a first-level queue based on membership in one of a plurality of first-level categories. The method further includes removing selected commands from the plurality of first-level queues according to a first schedule and performing at least one operation on the selected commands. The method further includes storing the selected commands among a plurality of second-level queues in the RAM. Each selected command is assigned to a second-level queue based on whether the command is a read command or a write command. The method further includes removing active commands from the plurality of second-level queues according to a second schedule. The method further includes issuing the active commands to a back end of the controller for processing.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Sancar Kunt Olcay, Dishi Lai
  • Patent number: 11042478
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing storage devices. In some implementations, a memory controller receives a logical write request over a logical interface that the memory controller provides for accessing a non-volatile storage device. The logical write request indicates a logical address at which to write data to the non-volatile storage device. In response to receiving the logical write request, the memory controller sends a write request event to a host system. The memory controller receives a physical write command from the host system over a physical interface that the memory controller provides for accessing the non-volatile storage device. In response to receiving the physical write command, the memory controller stores the data in the non-volatile storage device according to the physical write command.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 22, 2021
    Assignee: Google LLC
    Inventors: Christopher J. Sabol, Tomasz Jeznach
  • Patent number: 11036639
    Abstract: A cache apparatus is provided comprising a data storage structure providing N cache ways that each store data as a plurality of cache blocks. The data storage structure is organised as a plurality of sets, where each set comprises a cache block from each way, and further the data storage structure comprises a first data array and a second data array, where at least the second data array is set associative. A set associative tag storage structure stores a tag value for each cache block, with that set associative tag storage structure being shared by the first and second data arrays. Control circuitry applies an access likelihood policy to determine, for each set, a subset of the cache blocks of that set to be stored within the first data array.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 15, 2021
    Assignee: ARM Limited
    Inventors: Ricardo Daniel Queiros Alves, Nikos Nikoleris, Shidhartha Das, Andreas Lars Sandberg
  • Patent number: 11036435
    Abstract: Aspects of a storage device include a memory comprising a plurality of memory locations each associated with a physical address, the memory configured to store a plurality of video frames received from a host device at the physical addresses, each of the video frames being associated with a logical address; and a controller configured to store in a partition of the memory the logical addresses for a subset of the video frames, the controller being configured to provide the host access to the partition to read the logical addresses during rapid playback of the video frames. Aspects of the host device include a processor configured to write the video frames to the storage device, to identify the subset of the video frames to the storage device, and during rapid playback, to access the storage device to read the logical address for each video frame in the subset.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 15, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sridhar Prudvi Raj Gunda, Lalit Mohan Soni