Patents Examined by Reginald G. Bragdon
  • Patent number: 10387057
    Abstract: A memory system includes: a memory device including a plurality of memory blocks; and a controller including a memory, the controller being suitable for: selecting a source memory block and a target memory block among the plurality of memory blocks; loading map segments of map data for the source memory block on the memory; determining valid pages, among a plurality of pages included in the source memory block, through the map segments; loading valid data stored in the valid pages on the memory; updating map data for the valid data; and storing the valid data and the updated map data in a plurality of pages included in the target memory block.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10387331
    Abstract: A cache is maintained with write order numbers that indicate orders of writes into the cache, so that periodic partial flushes of the cache can be executed while maintaining write order consistency. A method of storing data into the cache includes receiving a request to write data into the cache, identifying lines in the cache for storing the data, writing the data into the lines of the cache, storing a write order number, and associating the write order number with the lines of the cache. A method of flushing a cache having cache lines associated with write order numbers includes the steps of identifying lines in the cache that are associated with either a selected write order number or a write order number that is less than the selected write order number, and flushing data stored in the identified lines to a persistent storage.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 20, 2019
    Assignee: VMWARE, INC.
    Inventors: Thomas A. Phelan, Erik Cota-Robles
  • Patent number: 10387321
    Abstract: In response to determining, by a storage controller, that a first process is to perform a write operation, a customer data track in a cache is configured for exclusive access while waiting for the write operation on the customer data track to be performed by the first process. In response to configuring the customer data track for the exclusive access, a copy of a metadata track is generated, wherein the metadata track stores metadata information of the customer data track and is configured for shared access. The copy of the metadata track is configured to provide exclusive access to a second process to perform operations on the copy of the metadata track, wherein the first process is able to perform the write operation on the customer data track that causes the metadata track to be updated while the second process performs the operations on the copy of the metadata track.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Beth A. Peterson
  • Patent number: 10387076
    Abstract: The invention introduces a method for scheduling data-programming tasks, performed by a processing unit, including at least the following steps. At least one task of an (i+1)-th batch is performed between directing an engine to perform a task of an i-th batch and reception of an outcome of the task of the i-th batch.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: August 20, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Shen-Ting Chiu
  • Patent number: 10380032
    Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATINOAL BUSINESS MACHINES CORPORATION
    Inventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
  • Patent number: 10379766
    Abstract: A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jan Van Lunteren
  • Patent number: 10380033
    Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
  • Patent number: 10372608
    Abstract: A split head invalidation system includes a first memory including a ring buffer, a second memory, and a processor in communication with the first memory. The processor includes a consumer processor and a producer processor. The consumer processor is configured to maintain a head and tail pointer, detect a request to copy a memory entry from the ring buffer, and consume the memory entry. Consuming the memory entry includes iteratively testing a value associated with the memory entry in a slot indicated by the head pointer, retrieving the respective memory entry from the slot, and advancing the head pointer to the next slot until reaching a threshold quantity of slots. Additionally, the consumer processor is configured to invalidate each slot from the head pointer to the tail pointer after reaching the threshold quantity.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 10372358
    Abstract: A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jan Van Lunteren
  • Patent number: 10372677
    Abstract: A cache management system for managing a plurality of intermediate data includes a processor and a memory having stored thereon instructions that cause the processor to perform identifying a new intermediate data to be accessed, loading the intermediate data from the memory in response to identifying the new intermediate data as one of the plurality of intermediate data, in response to not identifying the new intermediate data as one of the plurality of intermediate data, selecting a set of victim intermediate data to evict from the memory based on a plurality of scores associated with respective ones of the plurality of intermediate data, the scores being based on a score table, evicting the set of victim intermediate data from the memory, updating the score table based on the set of victim intermediate data, and adding the new intermediate data to the plurality of intermediate data stored in the memory.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhengyu Yang, Jiayin Wang, Thomas David Evans
  • Patent number: 10372329
    Abstract: Storage systems store data in a storage pool comprising storage devices or virtual devices. The storage pool may be allocated for a particular purpose. If a virtual device within the storage pool needs to be repurposed, the virtual device is removed from the storage pool. Data is moved from the removed virtual device to one or more target virtual devices. Segments of the source virtual device being removed are copied to target virtual devices. Mapping tables associating source segments with target segments are stored. If the storage system receives a request to access data stored on a virtual device that is removed, the storage system processes the mapping tables to determine where the data is stored.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 6, 2019
    Assignee: DELPHIX CORP.
    Inventors: Matthew Allan Ahrens, Alexander Warner Reece, George Raymond Wilson
  • Patent number: 10372337
    Abstract: A write request processing method and a memory controller, where the method includes, determining a second write request set, by the memory controller, after determining that a quantity of write requests in a to-be-scheduled first write request set is less than a quantity of unoccupied storage units in a memory, where the write request in the first write request set is located before a first memory barrier, where a write request in the second write request set is a log write request, and where the write request in the second write request set is located behind the first memory barrier. The memory controller sends the write request in the first write request set and the write request in the second write request set in parallel to different unoccupied storage units in the memory.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: August 6, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jiwu Shu, Long Sun, Yuangang Wang
  • Patent number: 10366007
    Abstract: A method comprises: receiving input data comprising a number of read and write uncached transactions, a transaction density, a number of active cores (N active cores) of the at least two cores, main memory address layout, and number of and an identifier for each of: banks and ranks in main memory, interconnects, cache pools, and memory controllers; defining all sets of active cores; defining up to N sets of memory pools; performing, for combinations of at least one set of active cores with each of at least one subset, the specified number of read and write uncached transactions with main memory at a specified transaction density for each defined combination of each active core combination and each defined memory pools; measuring the execution time of such performance for each combination; storing the execution time for each combination; and identifying at least one combination having a lower execution time.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 30, 2019
    Assignee: Honeywell International Inc.
    Inventors: Pavel Zaykov, Lucie Matusova
  • Patent number: 10365938
    Abstract: Systems and methods for managing data input/output operations are described that include virtual machines operating with a shared storage within a host. In such a system, a computer-implemented method is provided for dynamically provisioning cache storage while operating system applications continue to operate, including stalling the virtual machine's local cache storage operations, changing the provision of cache storage size; and resuming the operations of the virtual machine.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: July 30, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Vikram Joshi, Yang Luan, Manish R. Apte, Hrishikesh A. Vidwans, Michael F. Brown
  • Patent number: 10366015
    Abstract: A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first expression of number of times indicating the number of times the specific position of a specific loop is executed; generating second expression of number of times indicating the number of times the data of the access target is stored in the cache; generating third expression of number of times indicating the number of times the data of the access target is removed from the cache; generating fourth expression of number of times, from a generated conflict miss cause common expression, indicating the number of times the data of the access target is stored in the cache; and estimating a number of cache miss based on the difference between the first and the second expressions and the difference between the third and the forth expressions.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Masaki Arai
  • Patent number: 10365827
    Abstract: A processing device of a storage server that manages a plurality of physical storage devices arranged in a plurality of stripes receives a request to write data. The processing device determines a total number of available stripe units to satisfy the request, identifies one or more stripes of the plurality of stripes that collectively include at least the total number of available stripe units, allocates the one or more stripes to the request, and stores the data for the request in the available stripe units of the one or more stripes.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 30, 2019
    Assignee: Pavilion Data Systems, Inc.
    Inventors: Venkeepuram R. Satish, Muthukumar Ratty, Kiron Balkrishna Malwankar
  • Patent number: 10359969
    Abstract: Systems and methods for creating virtual machine snapshots. An example method comprises: receiving a request to create a snapshot of a virtual machine running on a host computer system; protecting from modification a plurality of virtual memory pages of the virtual machine; responsive to detecting an attempt to modify a virtual memory page of the plurality of memory pages, copying the virtual memory page to a queue residing in a random access memory (RAM) of the host computer system; making the virtual memory page writable; retrieving the virtual memory page from the queue; writing the virtual memory page to a disk of the host computer system; and responsive to exhausting the queue, completing creation of the snapshot of the virtual machine.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 23, 2019
    Assignee: Parallels International GmbH
    Inventors: Iurii Ovchinnikov, Alexey Koryakin, Denis Lamtsov, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10359966
    Abstract: A logical group of data blocks stored in a first node is migrated to a second node according to a method that includes determining a first metric for each logical group of data blocks stored in the first node, the first metric representing a total size of the data blocks in the logical group, determining a second metric for each logical group of data blocks stored in the first node, the second metric representing a total size of the data blocks in the logical group that are uniquely stored in the first node, and selecting a logical group of data blocks for migration from the first node to the second node based on the first metric and the second metric.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: July 23, 2019
    Assignee: VMware, Inc.
    Inventors: Jorge Guerra Delgado, Jin Zhang, Radhika Vullikanti, Abhishek Gupta
  • Patent number: 10353814
    Abstract: The present disclosure relates to a method and system for optimizing garbage collection in a storage device. In an embodiment, number of free pages, number of valid pages and number of invalid pages in each of one or more memory blocks in the storage device is determined by a memory management system. Further, at least one target memory block having minimum number of free pages, minimum number of valid pages and maximum number of invalid pages is identified among the one or more memory blocks. The step of determining the number of valid pages is iteratively repeated until the number of valid pages is less than or equal to the number of free pages in at least one of the one or more memory blocks. Finally, the at least one target memory block is recycled by the memory management system, thereby optimizing the garbage collection in the storage device.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: July 16, 2019
    Assignee: Wipro Limited
    Inventor: Manasa Ranjan Boitei
  • Patent number: 10353594
    Abstract: An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 16, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Yusuke Abe, Koji Yuasa, Toshihisa Arai