Patents Examined by Reginald G. Bragdon
  • Patent number: 11403226
    Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11397645
    Abstract: Systems and methods for durable storage of storage volume “snapshots” are provided. Snapshots are stored as collections of snapshot data objects. To improve the durability of snapshot storage, physical deletion of snapshot data objects may be delayed for a period of time after the snapshot data objects are marked for deletion. Lists of the stored snapshot data objects and the snapshot data objects that make up active snapshots may be periodically analyzed. If there are any snapshot data objects that are part of active snapshots and are not present in the list of stored snapshot data objects, the snapshot data objects may be recovered before they are physically deleted.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 26, 2022
    Assignee: Amazon Technologies, Inc.
    Inventor: Shengjie Quan
  • Patent number: 11397539
    Abstract: An apparatus comprises at least one processing device comprising a processor and a memory. The at least one processing device is configured to provision a first logical device on a first storage system, to configure the first logical device to support replication from the first storage system to a second storage system, and to initiate generation of a remote backup copy of a second logical device on the second storage system. In conjunction with performance of a verification process for the remote backup copy of the second logical device, the at least one processing device is configured to cause the first logical device to be paired with the remote backup copy of the second logical device, and to mount the first logical device so as to permit performance of the verification process for the remote backup copy utilizing data obtained from the remote backup copy via the first logical device.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 26, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sunil Kumar, Krishna Deepak Nuthakki, Arieh Don
  • Patent number: 11397675
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 26, 2022
    Assignee: Kioxia Corporation
    Inventors: Kenichiro Yoshii, Tetsuya Sunata, Daisuke Iwai
  • Patent number: 11392511
    Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes DRAM for storage of data, an IOMMU coupled to the DRAM, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the DRAM, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the DRAM pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the DRAM within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: David Koufaty, Rajesh Sankaran, Anna Trikalinou, Rupin Vakharwala
  • Patent number: 11392312
    Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Niccolo′ Righetti
  • Patent number: 11385810
    Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 12, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Deepanshu Dutta, Huai-Yuan Tseng
  • Patent number: 11385801
    Abstract: Offloading device management responsibilities from a storage device in an array of storage devices, including: retrieving, from the storage device, control information describing the state of one or more memory blocks in the storage device; and performing, in dependence upon the control information, a storage device management operation.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 12, 2022
    Assignee: PURE STORAGE, INC.
    Inventor: Eric D. Seppanen
  • Patent number: 11385823
    Abstract: Techniques for rebuilding a disk array involve, in response to receiving a message for rebuilding disk arrays in a storage system, determining a target disk that causes rebuilding. Such techniques further involve determining from the disk arrays a set of disk arrays related to the target disk, and generating subsets of disk arrays from the set of disk arrays, each subset including disk arrays that can be rebuilt in parallel. Such techniques further involve determining, based on a number of disks included in each subset, a target subset from the plurality of subsets, and rebuilding disk arrays in the target subset in parallel. Accordingly, a disk array that is most suitable for parallel rebuilding may be determined, and the process of rebuilding the disk array is sped up. Such techniques reduce the delay caused by performing rebuilding, and improve rebuilding efficiency.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: July 12, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Ke Yang, Zhenhua Zhao, Baote Zhuo, Zhihui Qiu, Sihang Xia
  • Patent number: 11372581
    Abstract: An information processing apparatus includes a control unit to execute a program, a first storage unit, a second storage unit, and an output unit. The first storage unit stores a first program to be executed by the control unit. The second storage unit stores a second program to be executed by the control unit. The output unit receives, from the control unit, a read command for reading the second program from the second storage unit. The output unit output, to the second storage unit, a corresponding command corresponding to the received read command and corresponding to an operation mode having been set to the output unit. Before transmitting, to the output unit, the read command for reading the second program from the second storage unit, the control unit sets the operation mode of the output unit according to the first program stored in the first storage unit.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 28, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Junichi Goda
  • Patent number: 11366594
    Abstract: Techniques for in-band locking of extents containing multiple pages of shared non-volatile data storage are disclosed in which inter-node lock request messages indicate both an individual page for which a lock is requested and the multi-page extent that contains that page. A page lock or an extent lock is granted to the requesting node based on the time since the last access to the extent by the node to which the request was sent. A generation number may be maintained in each node and stored in the per-extent lock table entries and per-page lock table entries such that pages accessed by a node within an extent while the extent is in extent-locked access mode may subsequently be accessed by the node during a page-locked access mode for the extent occurring after the extent-locked access mode ends based on page locks created by the node during the extent-locked access mode.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 21, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jason Raff, Shari Vietry, David Bernard
  • Patent number: 11366763
    Abstract: A controller, a memory system and an operating method thereof are disclosed. The controller controls a nonvolatile memory device and the nonvolatile memory includes a first memory module configured to store a plurality of pieces of map data read from the nonvolatile memory device; and a second memory module configured to cache map data having locality among map data received from the first memory module.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Patent number: 11360885
    Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paul Stonelake, Ning Chen, Fangfang Zhu, Alex Tang
  • Patent number: 11360706
    Abstract: A memory system includes: a memory device; a host interface suitable for receiving write commands and queueing the received write commands in an interface queue; a workload manager suitable for detecting, in a cache program mode, a mixed workload when a read count is greater than a first threshold value, the read count representing a number of read commands queued in the interface queue and the mixed workload representing receipt of a mix of read and write commands; a mode manager suitable for switching from the cache program mode to a normal program mode when the mixed workload is detected; and a processor suitable for processing write commands queued in a command queue in the cache program mode and processing write commands queued in the interface queue in the normal program mode when the mixed workload is detected.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Joo-Young Lee, Hoe-Seung Jung
  • Patent number: 11354200
    Abstract: One embodiment provides a system which facilitates organization of data. During operation, the system receives data associated with a logical block address (LBA) to be written to a non-volatile memory. The system stores, in a data structure, a mapping of a first physical block address (PBA) corresponding to the LBA to a first status for the data, wherein the first status indicates data validity and recovery being enabled for the data. Responsive to receiving a command to delete the data, the system modifies the first status to indicate data invalidity and recovery being enabled for the data. Responsive to receiving a command to recover the previously deleted data, the system modifies the first status to indicate data validity and recovery being enabled for the data.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 7, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11347428
    Abstract: Techniques for processing I/O operations may include: receiving, at a data storage system, a write operation that writes first data to a target logical address of a log, wherein the data storage system includes a first storage tier of rotating non-volatile storage devices and a second tier of non-volatile solid state storage devices; storing the first data of the target logical address in a first level cache; destaging the first data from the first level cache to a first physical storage location in the first storage tier; and determining, in accordance with first read activity information for the target logical address, whether to store the first data for the target logical address in a second level cache including at least a portion of the non-volatile solid state storage devices of the second tier. The second level cache is a content addressable caching layer that caches data based on read activity.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 31, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Nickolay A. Dalmatov, Assaf Natanzon
  • Patent number: 11347514
    Abstract: Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 31, 2022
    Assignee: Apple Inc.
    Inventors: Deepak Limaye, Brian R. Mestan, Gideon N. Levinsky
  • Patent number: 11340802
    Abstract: A memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a plurality of planes and performs a protection operation and a general operation on the plurality of planes. The controller controls an operation of the semiconductor memory device by transferring a Sudden Power Off (SPO) process command, which is generated in response to a Sudden Power Off (SPO) that occurs in the memory system, to the semiconductor memory device. The semiconductor memory device is configured to interrupt the general operations among operations performed on the plurality of planes in response to the SPO process command.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyo Jae Lee
  • Patent number: 11334256
    Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: May 17, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sahil Sharma, Nian Niles Yang, Phil Reusswig, Rohit Sehgal, Piyush A. Dhotre
  • Patent number: 11327904
    Abstract: System, methods, and other embodiments described herein relate to improving security of protected values in a memory. In one embodiment, a method includes, in response to receiving a write request indicating at least an item and a write value to write into the memory, determining whether a protected items list (PIL) indicates that the item is protected. The method includes replacing the write value of the write request with a protected value from the PIL that corresponds with the item when the item is listed in the PIL as being protected. The method further includes executing the write request to the memory.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: May 10, 2022
    Assignees: Denso International America, Inc., Denso Corporation
    Inventor: David M. West