Abstract: A RAID controller attached to a storage network can detect the presence of multiple pathways to the same physical storage device. A path collection module can dynamically maintain all valid pathways to all attached storage devices. A path selection module can automatically and dynamically balance and rebalance desired paths to each storage device so as to simultaneously optimize data flow and provide continuity of I/O service throughout the attached storage network.

Abstract: A method for snapshots with crash consistency is provided. The method includes indicating intent to create a snapshot of storage system contents associated with an existing snapshot copy identifier, responsive to confirmation that all of a plurality of distributed agents are in a snapshot creation mode. The method includes responding, with a new snapshot copy identifier that replaces the existing snapshot copy identifier, to one or more inquiries from the plurality of distributed agents regarding one or more I/O operations, after the indicating the intent to create the snapshot. The method includes creating the snapshot using the existing snapshot copy identifier and committing the snapshot, responsive to receiving responses from the plurality of distributed agents that service is complete for all I/O operations that started before the indicating the intent to create the snapshot or that are associated with the existing snapshot copy identifier.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.

Abstract: Systems and methods of managing data storage, on non-volatile memory (NVM) media, by at least one processor may include: receiving a first storage request, to store a first data block on the NVM media; storing content of the first data block on a cache memory module; scheduling a future movement action of the content of the first data block from the cache memory module to the NVM media; and moving, transmitting or copying the content of the first data block from the cache memory module to at least one NVM device of the NVM media, according to the scheduled movement action.

Abstract: Dynamic storage provisioning for nested clusters is disclosed. A hosted cluster (HC) storage provisioner, executing in a hosted cluster that is hosted by an infrastructure cluster (IC), receives a request to dynamically provision a hosted cluster (HC) persistent volume object that is coupled to a physical storage. The HC storage provisioner causes an IC control plane executing on the IC to generate IC volume metadata that is backed by a storage volume on the physical storage. The HC storage provisioner determines that the IC volume metadata has been generated. The HC storage provisioner creates HC volume metadata on the hosted cluster that is linked to the IC volume metadata, the HC volume metadata comprising an HC persistent volume object that represents a persistent volume for use by the hosted cluster that is backed, via the IC volume metadata, by the physical storage.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.

Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; a Page Walk Cache (PWC) for storing page directory entries; and a memory controller configured to control accesses to the memory devices. The processor in an embodiment is configured to send to the memory controller a page directory base and a plurality of memory offsets; and receive from the memory controller and store in the PWC at least one of the page directory entries. The memory controller is configured to: combine a first level page directory entry with a second level memory offset; read from memory a second page directory entry using the first level page directory entry and the second level memory offset; and send to the processor at least one of the page directory entries and a page table entry (PTE).

Abstract: Techniques for generating a model for predicting when different hybrid prefetcher configurations should be used are disclosed. Techniques for using the model to predict when different hybrid prefetcher configurations should be used are also disclosed. The techniques for generating the model include obtaining a set of input data, and generating trees based on the training data. Each tree is associated with a different hybrid prefetcher configuration and the trees output certainty scores for the associated hybrid prefetcher configuration based on hardware feature measurements. To decide on a hybrid prefetcher configuration to use, a prefetcher traverses multiple trees to obtain certainty scores for different hybrid prefetcher configurations and identifies a hybrid prefetcher configuration to used based on a comparison of the certainty scores.

Abstract: A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.

Abstract: A method includes the steps of storing non-header data into a plurality of logical pages (“Lpages”) of a non-volatile memory (“NVM”), each Lpage including a number of read units, wherein at least one of the read units is a spanning read unit that spans Lpage boundaries and includes a first byte of at least one Lpage starting in the read unit, storing, in each of the at least one spanning read units that include the first byte of the at least one Lpage starting in the read unit, an Lpage identification header per each of the at least one Lpages starting in the spanning read unit, each Lpage identification header identifying a location of the first byte of the respective Lpage starting within the respective spanning read unit, and locating an Lpage of data stored in the NVM by referring to an entry stored a flash memory controller map table.

Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described.

Abstract: Storage objects and targetless snaps of the storage objects are represented using a system replication data pointer table (SRT), direct index lookup (DIL) tables, and virtual replication data pointer tables (VRTs). The SRT is a system level track-based data structure that stores metadata indicative of the actual (physical layer) allocations for all targetless snapshots in a storage array. The size of the SRT in terms of total entries corresponds to the overall storage capacity of the managed drives of the storage array. Each utilized entry of the SRT includes backend metadata with a pointer to a managed drive and metadata that identifies the associated storage object and track via the VRTs and DIL tables. SRT metadata is created and discarded as backend allocations are utilized and freed so the SRT is a dynamic data structure that can efficiently adjust its size and corresponding memory requirements.

Abstract: A data processing system includes a host configured to handle data in response to an input received by the host, and a plurality of memory systems engaged with the host and configured to store or output the data in response to a request generated by the host. A first memory system among the plurality of memory systems can perform generation, erasure, or updating of metadata for the plurality of memory systems.

Abstract: Systems and methods for free memory hinting by virtual machines. An example method comprises: identifying, by a virtual machine running on a host computer system, a first memory page referenced by a free memory list maintained by the virtual machine; identifying a second memory page residing in a hinting buffer associated with the virtual machine; moving the second memory page to the free memory list; disassociating the first memory page from the free memory list; and notifying the host computer system of an identifier of the first memory page.

Abstract: An information processing apparatus includes a storage unit configured to store data, a write control unit configured to instruct the storage unit to write data, a calculation unit configured to calculate, for each of a plurality of writes of data to the storage unit, a data size estimated to be actually written to the storage unit, based on a write data size specified by the write control unit, and a notification unit configured to issue a notification based on a total of the data sizes calculated by the calculation unit.

Abstract: Techniques involve storing data. In particular, such techniques involve: obtaining first data to be stored; determining whether the first data is able to be compressed in a compression ratio exceeding a predetermined threshold; and storing, based on the determined result, the first data into a storage device. Accordingly, such techniques can execute corresponding processing for data in a predicted compression ratio, so as to store the data into a storage device. In this manner, such techniques can significantly cut down the overheads for processing data while minimizing a storage space required for storing data.

Abstract: Systems and methods are disclosed for command status polling at a flash queue of a non-volatile memory device. The flash queue may be configured to perform polling on the status of flash operations without direct oversight from the data storage controller or firmware. In certain embodiments, a flash queue circuit may be configured to receive, from a data storage controller of a nonvolatile solid state memory (NVSSM) data storage device, one or more commands to access a flash memory of the NVSSM data storage device, each command of the one or more commands including one or more instructions. The flash queue circuit may execute the one or more commands to access the flash memory, evaluate a status response from the flash memory at the flash queue circuit, and re-execute a sequence of instructions of the one or more commands based on the status response.

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

Abstract: According to certain aspects, a system includes a client device that includes a virtual machine (VM) executed by a hypervisor, a driver located within the hypervisor, and a data agent. The VM may include a virtual hard disk file and a change block bitmap file. According to some embodiments the driver intercepts write operations generated by the VM to store data in a sector, determines an identity of the sector based on the intercepted write operation, determines an entry in the change block bitmap file that corresponds with the first sector, and modifies the entry in the change block bitmap file to indicate that data in that sector has changed. The data agent may generate an incremental backup of the VM based on the change block bitmap file in response to an instruction from a storage manager, where the incremental backup includes the data in the sector where data was modified.

Abstract: A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.