Abstract: Various embodiments set forth techniques for free space management in a block store. The techniques include receiving a request to allocate one or more blocks in a block store, accessing a sparse hierarchical data structure to identify an allocator page identifying a region of a backing store having a greatest number of free blocks, and allocating the one or more blocks.

Abstract: An information processing apparatus includes: a first memory; a second memory different in processing speed from the first memory; and a processor including: a memory controller that is coupled to the first memory and the second memory and that controls an access to the first memory and an access to the second memory; and a plurality of controllers that access to the first memory or the second memory. The processor is configured to suppress a writing frequency of data into the second memory by controlling one or more first controllers that access the second memory among the plurality of controllers in accordance with a result of monitoring a state of writing the data into the second memory.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: Flexible deprovisioning of distributed storage is disclosed. For example, an orchestrator executes on a processor to measure a current storage demand factor based on a current count of service guests and a storage capacity of a plurality of storage nodes. A projected storage demand factor is calculated by (i) adjusting the current count of service guests with a timing factor resulting in a projected count, and (ii) combining the projected count with a storage class associated with the service guests. The orchestrator determines that the projected storage demand factor is lower than the current storage demand factor, and in response requests termination of a first storage node of the plurality of storage nodes based on the first storage node lacking an active communication session with the service guests. Cancel termination of the first storage node based on an association between the first storage node and a second storage node.

Abstract: A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.

Abstract: A semiconductor storage device includes a non-volatile first memory, a second memory that includes a first area for recording data to be recorded in the first memory and a second area for recording data read from the first memory, and a memory controller that controls the first memory.

Abstract: Disclosed is a memory system including a controller configured to authenticate a user who inputs a request for discarding the memory system, to verify whether the request is valid when the user is authenticated as a legitimate user, to register discard activation of the memory system when the request is valid, and to transmit the request to a memory device; and the memory device configured to determine whether the transmitted request is valid, and to register the discard activation of the memory system when the request is valid.

Abstract: A memory system may include a memory device including a first memory block group and a second memory block group; and a memory controller configured to designate a first memory block of memory blocks included in the first memory block group as an open block and designate a second memory block of memory blocks included in the second memory block group as the open block, and perform a program operation on the first and second memory blocks designated as the open blocks. When the first memory block designated as the open block is changed to a closed block, the memory controller may determine whether to designate a third memory block among the memory blocks included in the first or the second memory block group as a new open block based on a number of times voltage abnormalities have occurred on a voltage supplied to the memory device.

Abstract: Methods, systems, and apparatus for command scheduling in a memory subsystem according to a selected scheduling ordering are described. Scheduling orderings are determined for a set of commands, where a scheduling ordering identifies an order by which a memory subsystem controller is to issue each command in the set of commands to the memory device. Scores are calculated for the scheduling orderings. A score of the plurality of scores includes a measure of performance of execution of the set of commands according to the scheduling ordering. A scheduling ordering is selected from the scheduling orderings based on the scores, and a command is issued to the memory device according to the scheduling ordering.

Abstract: A method of labeling logic number units in a storage system results in the use of the same label for related LUNs in different storage arrays. A first storage array includes a first source logical unit number LUN, the second storage array includes a first target LUN, and the first source LUN and the first target LUN are a pair of active-active LUNs. The first storage array sends an assignable-address set of selectable labels for the first source LUN to the address assignment apparatus. The second storage array sends an assignable-address set of selectable labels for the first target LUN to the address assignment apparatus. The address assignment apparatus selects a label that is in both assignable-address sets of the first source LUN and first target LUN, and assign that selected label to both LUNs. Thereafter, the address assignment apparatus sends the selected label to the first storage array and the second storage array for identifying both the first source LUN and the first target LUN.

Abstract: Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.

Abstract: A method is provided that includes searching tags in a tag group comprised in a tagged memory system for an available tag line during a clock cycle, wherein the tagged memory system includes a plurality of tag lines having respective tags and wherein the tags are divided into a plurality of non-overlapping tag groups, and searching tags in a next tag group of the plurality of tag groups for an available tag line during a next clock cycle when the searching in the tag group does not find an available tag line.

Abstract: The present disclosure relates to a method, a device, and a computer program product for managing a storage system. The storage system includes a first control node, a second control node, and a persistent storage device, the first control node being in an activated state, and the second control node being in a state of transfer from a non-activated state to an activated state. A method includes: loading a first list of page descriptors of the storage system to the second control node to generate a second list of page descriptors at the second control node, the first list including a portion of multiple page descriptors of the storage system that has been modified but has not been flushed to the persistent storage device; receiving a synchronization message from the first control node that indicates that the first list has been modified by the first control node; and updating the second list at the second control node based on the synchronization message.

Abstract: A storage system in one embodiment comprises storage nodes, an address space, address mapping sub-journals and write cache data sub-journals. Each address mapping sub-journal corresponds to a slice of the address space, is under control of one of the storage nodes and comprises update information corresponding to updates to an address mapping data structure. Each write cache data sub journal is under control of the one of the storage nodes and comprises data pages to be later destaged to the address space. A given storage node is configured to store write cache metadata in a given address mapping sub journal that is under control of the given storage node. The write cache metadata corresponds to a given data page stored in a given write cache data sub-journal that is also under control of the given storage node.

Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.

Abstract: In one embodiment, a method includes receiving a stored copy request indicating data and including a request identifier, scheduling publication of the data to an object store, and sending a subscription request indicating the data and the request identifier to the object store. In another embodiment, a method includes receiving a publication request indicating data to be copied, wherein the publication request is a recording request indicating a channel and a timespan, receiving one or more subscription requests for the data, receiving the data, and generating a copy of the data for each subscription request.

Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.

Abstract: Metadata of extent-based storage systems can be managed. For example, a computing device can store a first metadata object and a second metadata object in a first memory device. The first metadata object can specify locations of a first set of extents corresponding to a first data unit stored in a second memory device. The second metadata object can specify locations of a second set of extents corresponding to a second data unit stored in the second memory device. The computing device can determine that a first size of the first metadata object is smaller than a second size of the second metadata object. The computing device can remove the second metadata object from the first memory device based on determining that the first size is less than the second size.

Abstract: An embodiment includes a system, comprising: a processor configured to: read a stride parameter from a device coupled to the processor; and map registers associated with the device into virtual memory based on the stride parameter; wherein: the stride parameter is configured to indicate a stride between the registers associated with the device; and the processor is configured to map at least one of the registers to user space virtual memory in response to the stride parameter.

Abstract: A method of managing an integrated circuit memory includes having an integrated circuit card with a memory space including memory space regions for storing user profile data. The memory space is partitioned into segments of memory space regions, where the segments of memory space regions includes allocated regions and empty regions. From the empty regions, the biggest empty region of the memory space is selected. The selected biggest empty region is widened by moving memory blocks positioned in a subset of allocated regions that are at boundaries of the selected biggest empty region into other available empty regions.